Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
Stephan Gerhold | f0ed728 | 2022-09-16 10:45:19 +0200 | [diff] [blame] | 9 | #include <platform_def.h> |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 10 | |
| 11 | #include <msm8916_mmap.h> |
| 12 | |
Stephan Gerhold | da60d6f | 2022-09-16 10:45:19 +0200 | [diff] [blame] | 13 | #if PLATFORM_CORE_COUNT > 1 |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 14 | #define APCS_TCM_START_ADDR 0x10 |
Stephan Gerhold | da60d6f | 2022-09-16 10:45:19 +0200 | [diff] [blame] | 15 | #else |
| 16 | #define APCS_TCM_START_ADDR 0x34 |
| 17 | #endif |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 18 | #define APCS_TCM_REDIRECT_EN_0 BIT_32(0) |
| 19 | |
| 20 | .globl plat_crash_console_init |
| 21 | .globl plat_crash_console_putc |
| 22 | .globl plat_crash_console_flush |
| 23 | .globl plat_panic_handler |
| 24 | .globl plat_my_core_pos |
| 25 | .globl plat_get_my_entrypoint |
| 26 | .globl plat_reset_handler |
| 27 | .globl platform_mem_init |
| 28 | .globl msm8916_entry_point |
| 29 | |
| 30 | /* ------------------------------------------------- |
| 31 | * int plat_crash_console_init(void) |
| 32 | * Initialize the crash console. |
| 33 | * Out: r0 - 1 on success, 0 on error |
| 34 | * Clobber list : r0 - r4 |
| 35 | * ------------------------------------------------- |
| 36 | */ |
| 37 | func plat_crash_console_init |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 38 | ldr r1, =BLSP_UART_BASE |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 39 | mov r0, #1 |
| 40 | b console_uartdm_core_init |
| 41 | endfunc plat_crash_console_init |
| 42 | |
| 43 | /* ------------------------------------------------- |
| 44 | * int plat_crash_console_putc(int c) |
| 45 | * Print a character on the crash console. |
| 46 | * In : r0 - character to be printed |
| 47 | * Out: r0 - printed character on success |
| 48 | * Clobber list : r1, r2 |
| 49 | * ------------------------------------------------- |
| 50 | */ |
| 51 | func plat_crash_console_putc |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 52 | ldr r1, =BLSP_UART_BASE |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 53 | b console_uartdm_core_putc |
| 54 | endfunc plat_crash_console_putc |
| 55 | |
| 56 | /* ------------------------------------------------- |
| 57 | * void plat_crash_console_flush(void) |
| 58 | * Force a write of all buffered data that has not |
| 59 | * been output. |
| 60 | * Clobber list : r1, r2 |
| 61 | * ------------------------------------------------- |
| 62 | */ |
| 63 | func plat_crash_console_flush |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 64 | ldr r1, =BLSP_UART_BASE |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 65 | b console_uartdm_core_flush |
| 66 | endfunc plat_crash_console_flush |
| 67 | |
| 68 | /* ------------------------------------------------- |
| 69 | * void plat_panic_handler(void) __dead |
| 70 | * Called when an unrecoverable error occurs. |
| 71 | * ------------------------------------------------- |
| 72 | */ |
| 73 | func plat_panic_handler |
| 74 | /* Try to shutdown/reset */ |
| 75 | ldr r0, =MPM_PS_HOLD |
| 76 | mov r1, #0 |
| 77 | str r1, [r0] |
| 78 | 1: b 1b |
| 79 | endfunc plat_panic_handler |
| 80 | |
| 81 | /* ------------------------------------------------- |
| 82 | * unsigned int plat_my_core_pos(void) |
| 83 | * Out: r0 - index of the calling CPU |
| 84 | * ------------------------------------------------- |
| 85 | */ |
| 86 | func plat_my_core_pos |
Stephan Gerhold | da60d6f | 2022-09-16 10:45:19 +0200 | [diff] [blame] | 87 | .if PLATFORM_CORE_COUNT > 1 |
| 88 | ldcopr r1, MPIDR |
| 89 | and r0, r1, #MPIDR_CPU_MASK |
| 90 | .if PLATFORM_CLUSTER_COUNT > 1 |
| 91 | and r1, r1, #MPIDR_CLUSTER_MASK |
| 92 | orr r0, r0, r1, LSR #(MPIDR_AFFINITY_BITS - \ |
| 93 | PLATFORM_CPU_PER_CLUSTER_SHIFT) |
| 94 | .endif |
| 95 | .else |
| 96 | /* There is just a single core so always 0 */ |
| 97 | mov r0, #0 |
Stephan Gerhold | f0ed728 | 2022-09-16 10:45:19 +0200 | [diff] [blame] | 98 | .endif |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 99 | bx lr |
| 100 | endfunc plat_my_core_pos |
| 101 | |
| 102 | /* ------------------------------------------------- |
| 103 | * uintptr_t plat_get_my_entrypoint(void) |
| 104 | * Distinguish cold and warm boot and return warm boot |
| 105 | * entry address if available. |
| 106 | * Out: r0 - warm boot entry point or 0 on cold boot |
| 107 | * ------------------------------------------------- |
| 108 | */ |
| 109 | func plat_get_my_entrypoint |
| 110 | ldr r0, =msm8916_entry_point |
| 111 | ldr r0, [r0] |
| 112 | cmp r0, #0 |
| 113 | bxne lr |
| 114 | |
| 115 | /* |
| 116 | * Cold boot: Disable TCM redirect to L2 cache as early as |
| 117 | * possible to avoid crashes when making use of the cache. |
| 118 | */ |
Stephan Gerhold | f0ed728 | 2022-09-16 10:45:19 +0200 | [diff] [blame] | 119 | ldr r1, =APCS_CFG(0) |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 120 | ldr r2, [r1, #APCS_TCM_START_ADDR] |
| 121 | and r2, r2, #~APCS_TCM_REDIRECT_EN_0 |
| 122 | str r2, [r1, #APCS_TCM_START_ADDR] |
| 123 | bx lr |
| 124 | endfunc plat_get_my_entrypoint |
| 125 | |
| 126 | /* ------------------------------------------------- |
| 127 | * void platform_mem_init(void) |
| 128 | * Performs additional memory initialization early |
| 129 | * in the boot process. |
| 130 | * ------------------------------------------------- |
| 131 | */ |
| 132 | func platform_mem_init |
| 133 | /* Nothing to do here, all memory is already initialized */ |
| 134 | bx lr |
| 135 | endfunc platform_mem_init |
| 136 | |
| 137 | .data |
| 138 | .align 3 |
| 139 | |
| 140 | /* ------------------------------------------------- |
| 141 | * Warm boot entry point for CPU. Set by PSCI code. |
| 142 | * ------------------------------------------------- |
| 143 | */ |
| 144 | msm8916_entry_point: |
| 145 | .word 0 |