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Jeenu Viswambharan5c503042017-05-26 14:15:40 +01001/*
Antonio Nino Diazfeacba32018-08-21 16:12:29 +01002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan5c503042017-05-26 14:15:40 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Daniel Boulby844b4872018-09-18 13:36:39 +01007#include <cdefs.h>
Antonio Nino Diazfeacba32018-08-21 16:12:29 +01008#include <stdbool.h>
Jeenu Viswambharan5c503042017-05-26 14:15:40 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <drivers/arm/smmu_v3.h>
11#include <lib/mmio.h>
12
Daniel Boulby844b4872018-09-18 13:36:39 +010013static inline uint32_t __init smmuv3_read_s_idr1(uintptr_t base)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010014{
15 return mmio_read_32(base + SMMU_S_IDR1);
16}
17
Daniel Boulby844b4872018-09-18 13:36:39 +010018static inline uint32_t __init smmuv3_read_s_init(uintptr_t base)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010019{
20 return mmio_read_32(base + SMMU_S_INIT);
21}
22
Daniel Boulby844b4872018-09-18 13:36:39 +010023static inline void __init smmuv3_write_s_init(uintptr_t base, uint32_t value)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010024{
25 mmio_write_32(base + SMMU_S_INIT, value);
26}
27
Antonio Nino Diazfeacba32018-08-21 16:12:29 +010028/* Test for pending invalidate */
29static inline bool smmuv3_inval_pending(uintptr_t base)
30{
31 return (smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK) != 0U;
32}
33
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010034/*
35 * Initialize the SMMU by invalidating all secure caches and TLBs.
36 *
37 * Returns 0 on success, and -1 on failure.
38 */
Daniel Boulby844b4872018-09-18 13:36:39 +010039int __init smmuv3_init(uintptr_t smmu_base)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010040{
41 uint32_t idr1_reg;
42
43 /*
44 * Invalidation of secure caches and TLBs is required only if the SMMU
45 * supports secure state. If not, it's implementation defined as to how
46 * SMMU_S_INIT register is accessed.
47 */
48 idr1_reg = smmuv3_read_s_idr1(smmu_base);
Antonio Nino Diazfeacba32018-08-21 16:12:29 +010049 if (((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) &
50 SMMU_S_IDR1_SECURE_IMPL_MASK) == 0U) {
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010051 return -1;
52 }
53
54 /* Initiate invalidation, and wait for it to finish */
55 smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK);
Antonio Nino Diazfeacba32018-08-21 16:12:29 +010056 while (smmuv3_inval_pending(smmu_base))
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010057 ;
58
59 return 0;
60}