Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 7 | #include <cdefs.h> |
Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 8 | #include <stdbool.h> |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/smmu_v3.h> |
| 11 | #include <lib/mmio.h> |
| 12 | |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 13 | static inline uint32_t __init smmuv3_read_s_idr1(uintptr_t base) |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 14 | { |
| 15 | return mmio_read_32(base + SMMU_S_IDR1); |
| 16 | } |
| 17 | |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 18 | static inline uint32_t __init smmuv3_read_s_init(uintptr_t base) |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 19 | { |
| 20 | return mmio_read_32(base + SMMU_S_INIT); |
| 21 | } |
| 22 | |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 23 | static inline void __init smmuv3_write_s_init(uintptr_t base, uint32_t value) |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 24 | { |
| 25 | mmio_write_32(base + SMMU_S_INIT, value); |
| 26 | } |
| 27 | |
Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 28 | /* Test for pending invalidate */ |
| 29 | static inline bool smmuv3_inval_pending(uintptr_t base) |
| 30 | { |
| 31 | return (smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK) != 0U; |
| 32 | } |
| 33 | |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 34 | /* |
| 35 | * Initialize the SMMU by invalidating all secure caches and TLBs. |
| 36 | * |
| 37 | * Returns 0 on success, and -1 on failure. |
| 38 | */ |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 39 | int __init smmuv3_init(uintptr_t smmu_base) |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 40 | { |
| 41 | uint32_t idr1_reg; |
| 42 | |
| 43 | /* |
| 44 | * Invalidation of secure caches and TLBs is required only if the SMMU |
| 45 | * supports secure state. If not, it's implementation defined as to how |
| 46 | * SMMU_S_INIT register is accessed. |
| 47 | */ |
| 48 | idr1_reg = smmuv3_read_s_idr1(smmu_base); |
Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 49 | if (((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) & |
| 50 | SMMU_S_IDR1_SECURE_IMPL_MASK) == 0U) { |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 51 | return -1; |
| 52 | } |
| 53 | |
| 54 | /* Initiate invalidation, and wait for it to finish */ |
| 55 | smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK); |
Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 56 | while (smmuv3_inval_pending(smmu_base)) |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 57 | ; |
| 58 | |
| 59 | return 0; |
| 60 | } |