Heiko Stuebner | 9e56bec | 2019-10-09 12:15:56 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <ddr_parameter.h> |
| 8 | #include <secure.h> |
| 9 | #include <px30_def.h> |
| 10 | |
| 11 | void secure_timer_init(void) |
| 12 | { |
| 13 | mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, |
| 14 | TIMER_DIS); |
| 15 | |
| 16 | mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); |
| 17 | mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); |
| 18 | |
| 19 | /* auto reload & enable the timer */ |
| 20 | mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, |
| 21 | TIMER_EN | TIMER_FMODE); |
| 22 | } |
| 23 | |
| 24 | void sgrf_init(void) |
| 25 | { |
| 26 | uint32_t i, val; |
| 27 | struct param_ddr_usage usg; |
| 28 | |
| 29 | /* general secure regions */ |
| 30 | usg = ddr_region_usage_parse(DDR_PARAM_BASE, |
| 31 | PLAT_MAX_DDR_CAPACITY_MB); |
| 32 | for (i = 0; i < usg.s_nr; i++) { |
| 33 | /* enable secure */ |
| 34 | val = mmio_read_32(FIREWALL_DDR_BASE + |
| 35 | FIREWALL_DDR_FW_DDR_CON_REG); |
| 36 | val |= BIT(7 - i); |
| 37 | mmio_write_32(FIREWALL_DDR_BASE + |
| 38 | FIREWALL_DDR_FW_DDR_CON_REG, val); |
| 39 | /* map top and base */ |
| 40 | mmio_write_32(FIREWALL_DDR_BASE + |
| 41 | FIREWALL_DDR_FW_DDR_RGN(7 - i), |
| 42 | RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); |
| 43 | } |
| 44 | |
| 45 | /* set ddr rgn0_top and rga0_top as 0 */ |
| 46 | mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); |
| 47 | |
| 48 | /* set all slave ip into no-secure, except stimer */ |
| 49 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); |
| 50 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); |
| 51 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); |
| 52 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); |
| 53 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); |
| 54 | |
| 55 | /* set master crypto to no-secure, dcf to secure */ |
| 56 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); |
| 57 | |
| 58 | /* set DMAC into no-secure */ |
| 59 | mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); |
| 60 | mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); |
| 61 | mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); |
| 62 | mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); |
| 63 | |
| 64 | /* soft reset dma before use */ |
| 65 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); |
| 66 | udelay(5); |
| 67 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); |
| 68 | } |