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Paul Beesleyf3653a62019-05-22 11:22:44 +01001NVIDIA Tegra
2============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Varun Wadekar13f57a82019-12-03 14:14:12 -08004- .. rubric:: T194
5 :name: t194
6
7T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
8configuration. The Carmel cores support the ARM Architecture version 8.2,
9executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel
10processors are organized as four dual-core clusters, where each cluster has
11a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects
12these processor complexes and allows heterogeneous multi-processing with all
13eight cores if required.
14
Varun Wadekar6801c792019-01-03 15:09:44 -080015- .. rubric:: T186
16 :name: t186
17
18The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous
19multi-processing (HMP) solution designed to optimize performance and
20efficiency.
21
22T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
23in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
24support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
25including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
26Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2
27unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
28Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
29high speed coherency fabric connects these two processor complexes and allows
30heterogeneous multi-processing with all six cores if required.
31
Douglas Raillardd7c21b72017-06-28 15:23:03 +010032- .. rubric:: T210
33 :name: t210
34
Dan Handley610e7e12018-03-01 18:44:00 +000035T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
36companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
37support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
38including legacy Armv7-A applications. The Cortex-A57 processors each have
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003948 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
40Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
41and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
42
43- .. rubric:: T132
44 :name: t132
45
46Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
Dan Handley610e7e12018-03-01 18:44:00 +000047fully Armv8-A architecture compatible. Each of the two Denver cores
Douglas Raillardd7c21b72017-06-28 15:23:03 +010048implements a 7-way superscalar microarchitecture (up to 7 concurrent
49micro-ops can be executed per clock), and includes a 128KB 4-way L1
50instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
51cache, which services both cores.
52
53Denver implements an innovative process called Dynamic Code Optimization,
54which optimizes frequently used software routines at runtime into dense,
55highly tuned microcode-equivalent routines. These are stored in a
56dedicated, 128MB main-memory-based optimization cache. After being read
57into the instruction cache, the optimized micro-ops are executed,
58re-fetched and executed from the instruction cache as long as needed and
59capacity allows.
60
61Effectively, this reduces the need to re-optimize the software routines.
62Instead of using hardware to extract the instruction-level parallelism
63(ILP) inherent in the code, Denver extracts the ILP once via software
64techniques, and then executes those routines repeatedly, thus amortizing
65the cost of ILP extraction over the many execution instances.
66
67Denver also features new low latency power-state transitions, in addition
68to extensive power-gating and dynamic voltage and clock scaling based on
69workloads.
70
71Directory structure
Paul Beesleyf3653a62019-05-22 11:22:44 +010072-------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010073
74- plat/nvidia/tegra/common - Common code for all Tegra SoCs
75- plat/nvidia/tegra/soc/txxx - Chip specific code
76
77Trusted OS dispatcher
Paul Beesleyf3653a62019-05-22 11:22:44 +010078---------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010079
Varun Wadekar6801c792019-01-03 15:09:44 -080080Tegra supports multiple Trusted OS'.
81
82- Trusted Little Kernel (TLK): In order to include the 'tlkd' dispatcher in
83 the image, pass 'SPD=tlkd' on the command line while preparing a bl31 image.
84- Trusty: In order to include the 'trusty' dispatcher in the image, pass
85 'SPD=trusty' on the command line while preparing a bl31 image.
86
87This allows other Trusted OS vendors to use the upstream code and include
88their dispatchers in the image without changing any makefiles.
89
90These are the supported Trusted OS' by Tegra platforms.
91
Varun Wadekar13f57a82019-12-03 14:14:12 -080092- Tegra132: TLK
93- Tegra210: TLK and Trusty
94- Tegra186: Trusty
95- Tegra194: Trusty
Douglas Raillardd7c21b72017-06-28 15:23:03 +010096
Varun Wadekar4d034c52019-01-11 14:47:48 -080097Scatter files
Paul Beesleyf3653a62019-05-22 11:22:44 +010098-------------
Varun Wadekar4d034c52019-01-11 14:47:48 -080099
100Tegra platforms currently support scatter files and ld.S scripts. The scatter
101files help support ARMLINK linker to generate BL31 binaries. For now, there
102exists a common scatter file, plat/nvidia/tegra/scat/bl31.scat, for all Tegra
103SoCs. The `LINKER` build variable needs to point to the ARMLINK binary for
104the scatter file to be used. Tegra platforms have verified BL31 image generation
105with ARMCLANG (compilation) and ARMLINK (linking) for the Tegra186 platforms.
106
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100107Preparing the BL31 image to run on Tegra SoCs
Paul Beesleyf3653a62019-05-22 11:22:44 +0100108---------------------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100109
110.. code:: shell
111
112 CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
Varun Wadekar13f57a82019-12-03 14:14:12 -0800113 TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd>
Varun Wadekar6801c792019-01-03 15:09:44 -0800114 bl31
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100115
116Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
117to the build command line.
118
119The Tegra platform code expects a pointer to the following platform specific
120structure via 'x1' register from the BL2 layer which is used by the
121bl31\_early\_platform\_setup() handler to extract the TZDRAM carveout base and
122size for loading the Trusted OS and the UART port ID to be used. The Tegra
123memory controller driver programs this base/size in order to restrict NS
124accesses.
125
126typedef struct plat\_params\_from\_bl2 {
127/\* TZ memory size */
128uint64\_t tzdram\_size;
129/* TZ memory base */
130uint64\_t tzdram\_base;
131/* UART port ID \*/
132int uart\_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800133/* L2 ECC parity protection disable flag \*/
134int l2\_ecc\_parity\_prot\_dis;
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700135/* SHMEM base address for storing the boot logs \*/
136uint64\_t boot\_profiler\_shmem\_base;
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137} plat\_params\_from\_bl2\_t;
138
139Power Management
Paul Beesleyf3653a62019-05-22 11:22:44 +0100140----------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100141
142The PSCI implementation expects each platform to expose the 'power state'
143parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field
144is implementation defined on Tegra SoCs and is preferably defined by
145tegra\_def.h.
146
147Tegra configs
Paul Beesleyf3653a62019-05-22 11:22:44 +0100148-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100149
150- 'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity
Dan Handley610e7e12018-03-01 18:44:00 +0000151 Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100152 be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit.