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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PLAT_PRIVATE_H
8#define PLAT_PRIVATE_H
Tony Xief6118cc2016-01-15 17:17:32 +08009
10#ifndef __ASSEMBLY__
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
Tony Xief6118cc2016-01-15 17:17:32 +080012#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
14#include <lib/psci/psci.h>
15#include <lib/xlat_tables/xlat_tables.h>
16#include <lib/mmio.h>
Tony Xief6118cc2016-01-15 17:17:32 +080017
Caesar Wangd90f43e2016-10-11 09:36:00 +080018#define __sramdata __attribute__((section(".sram.data")))
19#define __sramconst __attribute__((section(".sram.rodata")))
Lin Huang30e43392017-05-04 16:02:45 +080020#define __sramfunc __attribute__((section(".sram.text")))
21
22#define __pmusramdata __attribute__((section(".pmusram.data")))
23#define __pmusramconst __attribute__((section(".pmusram.rodata")))
24#define __pmusramfunc __attribute__((section(".pmusram.text")))
Caesar Wangd90f43e2016-10-11 09:36:00 +080025
26extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
27extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
Lin Huang30e43392017-05-04 16:02:45 +080028extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
Lin Huang88dd1232017-05-16 16:40:46 +080029extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
Xing Zheng93280b72016-10-26 21:25:26 +080030extern uint32_t __sram_incbin_start, __sram_incbin_end;
Lin Huang88dd1232017-05-16 16:40:46 +080031extern uint32_t __sram_incbin_real_end;
Caesar Wangd90f43e2016-10-11 09:36:00 +080032
Antonio Nino Diaz58230902018-09-24 17:16:20 +010033struct rockchip_bl31_params {
34 param_header_t h;
35 image_info_t *bl31_image_info;
36 entry_point_info_t *bl32_ep_info;
37 image_info_t *bl32_image_info;
38 entry_point_info_t *bl33_ep_info;
39 image_info_t *bl33_image_info;
40};
Tony Xief6118cc2016-01-15 17:17:32 +080041
42/******************************************************************************
43 * The register have write-mask bits, it is mean, if you want to set the bits,
44 * you needs set the write-mask bits at the same time,
45 * The write-mask bits is in high 16-bits.
46 * The fllowing macro definition helps access write-mask bits reg efficient!
47 ******************************************************************************/
48#define REG_MSK_SHIFT 16
49
Tony Xief6118cc2016-01-15 17:17:32 +080050#ifndef WMSK_BIT
51#define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT)
52#endif
53
54/* set one bit with write mask */
55#ifndef BIT_WITH_WMSK
56#define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
57#endif
58
59#ifndef BITS_SHIFT
60#define BITS_SHIFT(bits, shift) (bits << (shift))
61#endif
62
63#ifndef BITS_WITH_WMASK
Caesar Wang59e41b52016-04-10 14:11:07 +080064#define BITS_WITH_WMASK(bits, msk, shift)\
Tony Xief6118cc2016-01-15 17:17:32 +080065 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
66#endif
67
68/******************************************************************************
69 * Function and variable prototypes
70 *****************************************************************************/
71void plat_configure_mmu_el3(unsigned long total_base,
72 unsigned long total_size,
73 unsigned long,
74 unsigned long,
75 unsigned long,
76 unsigned long);
77
78void plat_cci_init(void);
79void plat_cci_enable(void);
80void plat_cci_disable(void);
81
82void plat_delay_timer_init(void);
83
Caesar Wang3e3c5b02016-05-25 19:03:04 +080084void params_early_setup(void *plat_params_from_bl2);
85
Tony Xief6118cc2016-01-15 17:17:32 +080086void plat_rockchip_gic_driver_init(void);
87void plat_rockchip_gic_init(void);
88void plat_rockchip_gic_cpuif_enable(void);
89void plat_rockchip_gic_cpuif_disable(void);
90void plat_rockchip_gic_pcpu_init(void);
91
Tony Xief6118cc2016-01-15 17:17:32 +080092void plat_rockchip_pmu_init(void);
93void plat_rockchip_soc_init(void);
Tony Xie42e113e2016-07-16 11:16:51 +080094uintptr_t plat_get_sec_entrypoint(void);
Tony Xief6118cc2016-01-15 17:17:32 +080095
Caesar Wang59e41b52016-04-10 14:11:07 +080096void platform_cpu_warmboot(void);
97
Caesar Wangef180072016-09-10 02:43:15 +080098struct gpio_info *plat_get_rockchip_gpio_reset(void);
99struct gpio_info *plat_get_rockchip_gpio_poweroff(void);
100struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
Caesar Wang5045a1c2016-09-10 02:47:53 +0800101struct apio_info *plat_get_rockchip_suspend_apio(void);
Caesar Wang038f6aa2016-05-25 19:21:43 +0800102void plat_rockchip_gpio_init(void);
Lin Huang2c60b5f2017-05-18 18:04:25 +0800103void plat_rockchip_save_gpio(void);
104void plat_rockchip_restore_gpio(void);
Caesar Wang038f6aa2016-05-25 19:21:43 +0800105
tony.xie422d51c2017-03-01 11:05:17 +0800106int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
107int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
108 plat_local_state_t lvl_state);
109int rockchip_soc_cores_pwr_dm_off(void);
110int rockchip_soc_sys_pwr_dm_suspend(void);
111int rockchip_soc_cores_pwr_dm_suspend(void);
112int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
113 plat_local_state_t lvl_state);
114int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
115 plat_local_state_t lvl_state);
116int rockchip_soc_cores_pwr_dm_on_finish(void);
117int rockchip_soc_sys_pwr_dm_resume(void);
118
119int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
120 plat_local_state_t lvl_state);
121int rockchip_soc_cores_pwr_dm_resume(void);
122void __dead2 rockchip_soc_soft_reset(void);
123void __dead2 rockchip_soc_system_off(void);
124void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
125 const psci_power_state_t *target_state);
126void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
127
Tony Xief6118cc2016-01-15 17:17:32 +0800128extern const unsigned char rockchip_power_domain_tree_desc[];
129
Lin Huang30e43392017-05-04 16:02:45 +0800130extern void *pmu_cpuson_entrypoint;
Tony Xief6118cc2016-01-15 17:17:32 +0800131extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT];
132extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
133
134extern const mmap_region_t plat_rk_mmap[];
Caesar Wangd90f43e2016-10-11 09:36:00 +0800135
Lin Huang30e43392017-05-04 16:02:45 +0800136void rockchip_plat_mmu_el3(void);
Caesar Wangd90f43e2016-10-11 09:36:00 +0800137
Tony Xief6118cc2016-01-15 17:17:32 +0800138#endif /* __ASSEMBLY__ */
139
Tony Xie42e113e2016-07-16 11:16:51 +0800140/******************************************************************************
141 * cpu up status
142 * The bits of macro value is not more than 12 bits for cmp instruction!
143 ******************************************************************************/
144#define PMU_CPU_HOTPLUG 0xf00
145#define PMU_CPU_AUTO_PWRDN 0xf0
146#define PMU_CLST_RET 0xa5
Tony Xief6118cc2016-01-15 17:17:32 +0800147
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000148#endif /* PLAT_PRIVATE_H */