blob: 4d2a5fc9f5ecd911e544a40e63992296a0ffb9bd [file] [log] [blame]
Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Antonio Nino Diazac998032017-02-27 17:23:54 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
7#ifndef __ARCH_H__
8#define __ARCH_H__
9
Isla Mitchell02c63072017-07-21 14:44:36 +010010#include <utils_def.h>
11
Soby Mathewc6820d12016-05-09 17:49:55 +010012/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
15#define MIDR_IMPL_MASK 0xff
16#define MIDR_IMPL_SHIFT 24
17#define MIDR_VAR_SHIFT 20
18#define MIDR_VAR_BITS 4
19#define MIDR_REV_SHIFT 0
20#define MIDR_REV_BITS 4
21#define MIDR_PN_MASK 0xfff
22#define MIDR_PN_SHIFT 4
23
24/*******************************************************************************
25 * MPIDR macros
26 ******************************************************************************/
Summer Qin93c812f2017-02-28 16:46:17 +000027#define MPIDR_MT_MASK (1 << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +010028#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
29#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
30#define MPIDR_AFFINITY_BITS 8
31#define MPIDR_AFFLVL_MASK 0xff
32#define MPIDR_AFFLVL_SHIFT 3
33#define MPIDR_AFF0_SHIFT 0
34#define MPIDR_AFF1_SHIFT 8
35#define MPIDR_AFF2_SHIFT 16
36#define MPIDR_AFFINITY_MASK 0x00ffffff
37#define MPIDR_AFFLVL0 0
38#define MPIDR_AFFLVL1 1
39#define MPIDR_AFFLVL2 2
40
41#define MPIDR_AFFLVL0_VAL(mpidr) \
42 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
43#define MPIDR_AFFLVL1_VAL(mpidr) \
44 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
45#define MPIDR_AFFLVL2_VAL(mpidr) \
46 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010047#define MPIDR_AFFLVL3_VAL(mpidr) 0
Soby Mathewc6820d12016-05-09 17:49:55 +010048
49/*
50 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
51 * add one while using this macro to define array sizes.
52 */
53#define MPIDR_MAX_AFFLVL 2
54
55/* Data Cache set/way op type defines */
56#define DC_OP_ISW 0x0
57#define DC_OP_CISW 0x1
58#define DC_OP_CSW 0x2
59
60/*******************************************************************************
61 * Generic timer memory mapped registers & offsets
62 ******************************************************************************/
63#define CNTCR_OFF 0x000
64#define CNTFID_OFF 0x020
65
66#define CNTCR_EN (1 << 0)
67#define CNTCR_HDBG (1 << 1)
68#define CNTCR_FCREQ(x) ((x) << 8)
69
70/*******************************************************************************
71 * System register bit definitions
72 ******************************************************************************/
73/* CLIDR definitions */
74#define LOUIS_SHIFT 21
75#define LOC_SHIFT 24
76#define CLIDR_FIELD_WIDTH 3
77
78/* CSSELR definitions */
79#define LEVEL_SHIFT 1
80
Dimitris Papastamosdda48b02017-10-17 14:03:14 +010081/* ID_PFR0 definitions */
82#define ID_PFR0_AMU_SHIFT U(20)
83#define ID_PFR0_AMU_LENGTH U(4)
84#define ID_PFR0_AMU_MASK U(0xf)
85
Soby Mathewc6820d12016-05-09 17:49:55 +010086/* ID_PFR1 definitions */
87#define ID_PFR1_VIRTEXT_SHIFT 12
88#define ID_PFR1_VIRTEXT_MASK 0xf
89#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
90 & ID_PFR1_VIRTEXT_MASK)
91#define ID_PFR1_GIC_SHIFT 28
92#define ID_PFR1_GIC_MASK 0xf
93
94/* SCTLR definitions */
Etienne Carriere70a004b2017-11-05 22:56:03 +010095#define SCTLR_RES1_DEF ((1 << 23) | (1 << 22) | (1 << 4) | (1 << 3))
96#if ARM_ARCH_MAJOR == 7
97#define SCTLR_RES1 SCTLR_RES1_DEF
98#else
99#define SCTLR_RES1 (SCTLR_RES1_DEF | (1 << 11))
100#endif
Soby Mathewc6820d12016-05-09 17:49:55 +0100101#define SCTLR_M_BIT (1 << 0)
102#define SCTLR_A_BIT (1 << 1)
103#define SCTLR_C_BIT (1 << 2)
104#define SCTLR_CP15BEN_BIT (1 << 5)
105#define SCTLR_ITD_BIT (1 << 7)
Etienne Carriere70a004b2017-11-05 22:56:03 +0100106#define SCTLR_Z_BIT (1 << 11)
Soby Mathewc6820d12016-05-09 17:49:55 +0100107#define SCTLR_I_BIT (1 << 12)
108#define SCTLR_V_BIT (1 << 13)
Etienne Carriere70a004b2017-11-05 22:56:03 +0100109#define SCTLR_RR_BIT (1 << 14)
Soby Mathewc6820d12016-05-09 17:49:55 +0100110#define SCTLR_NTWI_BIT (1 << 16)
111#define SCTLR_NTWE_BIT (1 << 18)
112#define SCTLR_WXN_BIT (1 << 19)
113#define SCTLR_UWXN_BIT (1 << 20)
114#define SCTLR_EE_BIT (1 << 25)
115#define SCTLR_TRE_BIT (1 << 28)
116#define SCTLR_AFE_BIT (1 << 29)
117#define SCTLR_TE_BIT (1 << 30)
David Cunadofee86532017-04-13 22:38:29 +0100118#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
119 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
Soby Mathewc6820d12016-05-09 17:49:55 +0100120
dp-arm595d0d52017-02-08 11:51:50 +0000121/* SDCR definitions */
122#define SDCR_SPD(x) ((x) << 14)
123#define SDCR_SPD_LEGACY 0x0
124#define SDCR_SPD_DISABLE 0x2
125#define SDCR_SPD_ENABLE 0x3
David Cunadofee86532017-04-13 22:38:29 +0100126#define SDCR_RESET_VAL 0x0
dp-arm595d0d52017-02-08 11:51:50 +0000127
David Cunadofee86532017-04-13 22:38:29 +0100128#if !ERROR_DEPRECATED
dp-arm595d0d52017-02-08 11:51:50 +0000129#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
David Cunadofee86532017-04-13 22:38:29 +0100130#endif
dp-arm595d0d52017-02-08 11:51:50 +0000131
Soby Mathewc6820d12016-05-09 17:49:55 +0100132/* HSCTLR definitions */
133#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \
134 | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \
Soby Mathewa993c422016-09-29 14:15:57 +0100135 | (1 << 3))
Soby Mathewc6820d12016-05-09 17:49:55 +0100136#define HSCTLR_M_BIT (1 << 0)
137#define HSCTLR_A_BIT (1 << 1)
138#define HSCTLR_C_BIT (1 << 2)
139#define HSCTLR_CP15BEN_BIT (1 << 5)
140#define HSCTLR_ITD_BIT (1 << 7)
141#define HSCTLR_SED_BIT (1 << 8)
142#define HSCTLR_I_BIT (1 << 12)
143#define HSCTLR_WXN_BIT (1 << 19)
144#define HSCTLR_EE_BIT (1 << 25)
145#define HSCTLR_TE_BIT (1 << 30)
146
147/* CPACR definitions */
148#define CPACR_FPEN(x) ((x) << 20)
149#define CPACR_FP_TRAP_PL0 0x1
150#define CPACR_FP_TRAP_ALL 0x2
151#define CPACR_FP_TRAP_NONE 0x3
152
153/* SCR definitions */
154#define SCR_TWE_BIT (1 << 13)
155#define SCR_TWI_BIT (1 << 12)
156#define SCR_SIF_BIT (1 << 9)
157#define SCR_HCE_BIT (1 << 8)
158#define SCR_SCD_BIT (1 << 7)
159#define SCR_NET_BIT (1 << 6)
160#define SCR_AW_BIT (1 << 5)
161#define SCR_FW_BIT (1 << 4)
162#define SCR_EA_BIT (1 << 3)
163#define SCR_FIQ_BIT (1 << 2)
164#define SCR_IRQ_BIT (1 << 1)
165#define SCR_NS_BIT (1 << 0)
166#define SCR_VALID_BIT_MASK 0x33ff
David Cunadofee86532017-04-13 22:38:29 +0100167#define SCR_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100168
169#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
170
171/* HCR definitions */
172#define HCR_AMO_BIT (1 << 5)
173#define HCR_IMO_BIT (1 << 4)
174#define HCR_FMO_BIT (1 << 3)
David Cunadofee86532017-04-13 22:38:29 +0100175#define HCR_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100176
177/* CNTHCTL definitions */
David Cunadofee86532017-04-13 22:38:29 +0100178#define CNTHCTL_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100179#define PL1PCEN_BIT (1 << 1)
180#define PL1PCTEN_BIT (1 << 0)
181
182/* CNTKCTL definitions */
183#define PL0PTEN_BIT (1 << 9)
184#define PL0VTEN_BIT (1 << 8)
185#define PL0PCTEN_BIT (1 << 0)
186#define PL0VCTEN_BIT (1 << 1)
187#define EVNTEN_BIT (1 << 2)
188#define EVNTDIR_BIT (1 << 3)
189#define EVNTI_SHIFT 4
190#define EVNTI_MASK 0xf
191
192/* HCPTR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100193#define HCPTR_RES1 ((1 << 13) | (1<<12) | 0x3ff)
Soby Mathewc6820d12016-05-09 17:49:55 +0100194#define TCPAC_BIT (1 << 31)
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100195#define TAM_BIT (1 << 30)
Soby Mathewc6820d12016-05-09 17:49:55 +0100196#define TTA_BIT (1 << 20)
197#define TCP11_BIT (1 << 10)
198#define TCP10_BIT (1 << 10)
David Cunadofee86532017-04-13 22:38:29 +0100199#define HCPTR_RESET_VAL HCPTR_RES1
200
201/* VTTBR defintions */
202#define VTTBR_RESET_VAL ULL(0x0)
203#define VTTBR_VMID_MASK ULL(0xff)
204#define VTTBR_VMID_SHIFT 48
205#define VTTBR_BADDR_MASK 0xffffffffffff
206#define VTTBR_BADDR_SHIFT 0
207
208/* HDCR definitions */
209#define HDCR_RESET_VAL 0x0
210
211/* HSTR definitions */
212#define HSTR_RESET_VAL 0x0
213
214/* CNTHP_CTL definitions */
215#define CNTHP_CTL_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100216
217/* NASCR definitions */
218#define NSASEDIS_BIT (1 << 15)
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100219#define NSTRCDIS_BIT (1 << 20)
David Cunadofee86532017-04-13 22:38:29 +0100220/* NOTE: correct typo in the definitions */
221#if !ERROR_DEPRECATED
Soby Mathewc6820d12016-05-09 17:49:55 +0100222#define NASCR_CP11_BIT (1 << 11)
223#define NASCR_CP10_BIT (1 << 10)
David Cunadofee86532017-04-13 22:38:29 +0100224#endif
225#define NSACR_CP11_BIT (1 << 11)
226#define NSACR_CP10_BIT (1 << 10)
227#define NSACR_IMP_DEF_MASK (0x7 << 16)
228#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
229#define NSACR_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100230
231/* CPACR definitions */
232#define ASEDIS_BIT (1 << 31)
233#define TRCDIS_BIT (1 << 28)
234#define CPACR_CP11_SHIFT 22
235#define CPACR_CP10_SHIFT 20
236#define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\
237 0x3 << CPACR_CP10_SHIFT)
David Cunadofee86532017-04-13 22:38:29 +0100238#define CPACR_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100239
240/* FPEXC definitions */
David Cunadofee86532017-04-13 22:38:29 +0100241#define FPEXC_RES1 ((1 << 10) | (1 << 9) | (1 << 8))
Soby Mathewc6820d12016-05-09 17:49:55 +0100242#define FPEXC_EN_BIT (1 << 30)
David Cunadofee86532017-04-13 22:38:29 +0100243#define FPEXC_RESET_VAL FPEXC_RES1
Soby Mathewc6820d12016-05-09 17:49:55 +0100244
245/* SPSR/CPSR definitions */
246#define SPSR_FIQ_BIT (1 << 0)
247#define SPSR_IRQ_BIT (1 << 1)
248#define SPSR_ABT_BIT (1 << 2)
249#define SPSR_AIF_SHIFT 6
250#define SPSR_AIF_MASK 0x7
251
252#define SPSR_E_SHIFT 9
253#define SPSR_E_MASK 0x1
254#define SPSR_E_LITTLE 0
255#define SPSR_E_BIG 1
256
257#define SPSR_T_SHIFT 5
258#define SPSR_T_MASK 0x1
259#define SPSR_T_ARM 0
260#define SPSR_T_THUMB 1
261
262#define SPSR_MODE_SHIFT 0
263#define SPSR_MODE_MASK 0x7
264
265
266#define DISABLE_ALL_EXCEPTIONS \
267 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
268
269/*
270 * TTBCR definitions
271 */
272/* The ARM Trusted Firmware uses the long descriptor format */
273#define TTBCR_EAE_BIT (1 << 31)
274
275#define TTBCR_SH1_NON_SHAREABLE (0x0 << 28)
276#define TTBCR_SH1_OUTER_SHAREABLE (0x2 << 28)
277#define TTBCR_SH1_INNER_SHAREABLE (0x3 << 28)
278
279#define TTBCR_RGN1_OUTER_NC (0x0 << 26)
280#define TTBCR_RGN1_OUTER_WBA (0x1 << 26)
281#define TTBCR_RGN1_OUTER_WT (0x2 << 26)
282#define TTBCR_RGN1_OUTER_WBNA (0x3 << 26)
283
284#define TTBCR_RGN1_INNER_NC (0x0 << 24)
285#define TTBCR_RGN1_INNER_WBA (0x1 << 24)
286#define TTBCR_RGN1_INNER_WT (0x2 << 24)
287#define TTBCR_RGN1_INNER_WBNA (0x3 << 24)
288
289#define TTBCR_EPD1_BIT (1 << 23)
290#define TTBCR_A1_BIT (1 << 22)
291
292#define TTBCR_T1SZ_SHIFT 16
293#define TTBCR_T1SZ_MASK (0x7)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100294#define TTBCR_TxSZ_MIN 0
295#define TTBCR_TxSZ_MAX 7
Soby Mathewc6820d12016-05-09 17:49:55 +0100296
297#define TTBCR_SH0_NON_SHAREABLE (0x0 << 12)
298#define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12)
299#define TTBCR_SH0_INNER_SHAREABLE (0x3 << 12)
300
301#define TTBCR_RGN0_OUTER_NC (0x0 << 10)
302#define TTBCR_RGN0_OUTER_WBA (0x1 << 10)
303#define TTBCR_RGN0_OUTER_WT (0x2 << 10)
304#define TTBCR_RGN0_OUTER_WBNA (0x3 << 10)
305
306#define TTBCR_RGN0_INNER_NC (0x0 << 8)
307#define TTBCR_RGN0_INNER_WBA (0x1 << 8)
308#define TTBCR_RGN0_INNER_WT (0x2 << 8)
309#define TTBCR_RGN0_INNER_WBNA (0x3 << 8)
310
311#define TTBCR_EPD0_BIT (1 << 7)
312#define TTBCR_T0SZ_SHIFT 0
313#define TTBCR_T0SZ_MASK (0x7)
314
315#define MODE_RW_SHIFT 0x4
316#define MODE_RW_MASK 0x1
317#define MODE_RW_32 0x1
318
319#define MODE32_SHIFT 0
320#define MODE32_MASK 0x1f
321#define MODE32_usr 0x10
322#define MODE32_fiq 0x11
323#define MODE32_irq 0x12
324#define MODE32_svc 0x13
325#define MODE32_mon 0x16
326#define MODE32_abt 0x17
327#define MODE32_hyp 0x1a
328#define MODE32_und 0x1b
329#define MODE32_sys 0x1f
330
331#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
332
333#define SPSR_MODE32(mode, isa, endian, aif) \
334 (MODE_RW_32 << MODE_RW_SHIFT | \
335 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
336 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
337 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
338 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
339
340/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100341 * TTBR definitions
342 */
343#define TTBR_CNP_BIT 0x1
344
345/*
Soby Mathewc6820d12016-05-09 17:49:55 +0100346 * CTR definitions
347 */
348#define CTR_CWG_SHIFT 24
349#define CTR_CWG_MASK 0xf
350#define CTR_ERG_SHIFT 20
351#define CTR_ERG_MASK 0xf
352#define CTR_DMINLINE_SHIFT 16
353#define CTR_DMINLINE_WIDTH 4
354#define CTR_DMINLINE_MASK ((1 << 4) - 1)
355#define CTR_L1IP_SHIFT 14
356#define CTR_L1IP_MASK 0x3
357#define CTR_IMINLINE_SHIFT 0
358#define CTR_IMINLINE_MASK 0xf
359
360#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
361
David Cunado5f55e282016-10-31 17:37:34 +0000362/* PMCR definitions */
363#define PMCR_N_SHIFT 11
364#define PMCR_N_MASK 0x1f
365#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
David Cunado4168f2f2017-10-02 17:41:39 +0100366#define PMCR_LC_BIT (1 << 6)
367#define PMCR_DP_BIT (1 << 5)
David Cunado5f55e282016-10-31 17:37:34 +0000368
Soby Mathewc6820d12016-05-09 17:49:55 +0100369/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000370 * Definitions of register offsets, fields and macros for CPU system
371 * instructions.
372 ******************************************************************************/
373
374#define TLBI_ADDR_SHIFT 0
375#define TLBI_ADDR_MASK 0xFFFFF000
376#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
377
378/*******************************************************************************
Soby Mathewc6820d12016-05-09 17:49:55 +0100379 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
380 * system level implementation of the Generic Timer.
381 ******************************************************************************/
382#define CNTNSAR 0x4
383#define CNTNSAR_NS_SHIFT(x) (x)
384
385#define CNTACR_BASE(x) (0x40 + ((x) << 2))
386#define CNTACR_RPCT_SHIFT 0x0
387#define CNTACR_RVCT_SHIFT 0x1
388#define CNTACR_RFRQ_SHIFT 0x2
389#define CNTACR_RVOFF_SHIFT 0x3
390#define CNTACR_RWVT_SHIFT 0x4
391#define CNTACR_RWPT_SHIFT 0x5
392
393/* MAIR macros */
394#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
395#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3))
396
397/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
398#define SCR p15, 0, c1, c1, 0
399#define SCTLR p15, 0, c1, c0, 0
Etienne Carriere70a004b2017-11-05 22:56:03 +0100400#define ACTLR p15, 0, c1, c0, 1
dp-arm595d0d52017-02-08 11:51:50 +0000401#define SDCR p15, 0, c1, c3, 1
Soby Mathewc6820d12016-05-09 17:49:55 +0100402#define MPIDR p15, 0, c0, c0, 5
403#define MIDR p15, 0, c0, c0, 0
404#define VBAR p15, 0, c12, c0, 0
405#define MVBAR p15, 0, c12, c0, 1
406#define NSACR p15, 0, c1, c1, 2
407#define CPACR p15, 0, c1, c0, 2
408#define DCCIMVAC p15, 0, c7, c14, 1
409#define DCCMVAC p15, 0, c7, c10, 1
410#define DCIMVAC p15, 0, c7, c6, 1
411#define DCCISW p15, 0, c7, c14, 2
412#define DCCSW p15, 0, c7, c10, 2
413#define DCISW p15, 0, c7, c6, 2
414#define CTR p15, 0, c0, c0, 1
415#define CNTFRQ p15, 0, c14, c0, 0
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100416#define ID_PFR0 p15, 0, c0, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100417#define ID_PFR1 p15, 0, c0, c1, 1
418#define MAIR0 p15, 0, c10, c2, 0
419#define MAIR1 p15, 0, c10, c2, 1
420#define TTBCR p15, 0, c2, c0, 2
421#define TTBR0 p15, 0, c2, c0, 0
422#define TTBR1 p15, 0, c2, c0, 1
423#define TLBIALL p15, 0, c8, c7, 0
424#define TLBIALLIS p15, 0, c8, c3, 0
425#define TLBIMVA p15, 0, c8, c7, 1
426#define TLBIMVAA p15, 0, c8, c7, 3
Antonio Nino Diazac998032017-02-27 17:23:54 +0000427#define TLBIMVAAIS p15, 0, c8, c3, 3
428#define BPIALLIS p15, 0, c7, c1, 6
Soby Mathewc6820d12016-05-09 17:49:55 +0100429#define HSCTLR p15, 4, c1, c0, 0
430#define HCR p15, 4, c1, c1, 0
431#define HCPTR p15, 4, c1, c1, 2
David Cunadofee86532017-04-13 22:38:29 +0100432#define HSTR p15, 4, c1, c1, 3
Soby Mathewc6820d12016-05-09 17:49:55 +0100433#define CNTHCTL p15, 4, c14, c1, 0
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000434#define CNTKCTL p15, 0, c14, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100435#define VPIDR p15, 4, c0, c0, 0
436#define VMPIDR p15, 4, c0, c0, 5
437#define ISR p15, 0, c12, c1, 0
438#define CLIDR p15, 1, c0, c0, 1
439#define CSSELR p15, 2, c0, c0, 0
440#define CCSIDR p15, 1, c0, c0, 0
Yatharth Kochara9f776c2016-11-10 16:17:51 +0000441#define DBGOSDLR p14, 0, c1, c3, 4
Soby Mathewc6820d12016-05-09 17:49:55 +0100442
David Cunado5f55e282016-10-31 17:37:34 +0000443/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
444#define HDCR p15, 4, c1, c1, 1
David Cunado5f55e282016-10-31 17:37:34 +0000445#define PMCR p15, 0, c9, c12, 0
David Cunadoc14b08e2016-11-25 00:21:59 +0000446#define CNTHP_CTL p15, 4, c14, c2, 1
David Cunado5f55e282016-10-31 17:37:34 +0000447
Etienne Carriere70a004b2017-11-05 22:56:03 +0100448/* AArch32 coproc registers for 32bit MMU descriptor support */
449#define PRRR p15, 0, c10, c2, 0
450#define NMRR p15, 0, c10, c2, 1
451#define DACR p15, 0, c3, c0, 0
452
Soby Mathewc6820d12016-05-09 17:49:55 +0100453/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
454#define ICC_IAR1 p15, 0, c12, c12, 0
455#define ICC_IAR0 p15, 0, c12, c8, 0
456#define ICC_EOIR1 p15, 0, c12, c12, 1
457#define ICC_EOIR0 p15, 0, c12, c8, 1
458#define ICC_HPPIR1 p15, 0, c12, c12, 2
459#define ICC_HPPIR0 p15, 0, c12, c8, 2
460#define ICC_BPR1 p15, 0, c12, c12, 3
461#define ICC_BPR0 p15, 0, c12, c8, 3
462#define ICC_DIR p15, 0, c12, c11, 1
463#define ICC_PMR p15, 0, c4, c6, 0
464#define ICC_RPR p15, 0, c12, c11, 3
465#define ICC_CTLR p15, 0, c12, c12, 4
466#define ICC_MCTLR p15, 6, c12, c12, 4
467#define ICC_SRE p15, 0, c12, c12, 5
468#define ICC_HSRE p15, 4, c12, c9, 5
469#define ICC_MSRE p15, 6, c12, c12, 5
470#define ICC_IGRPEN0 p15, 0, c12, c12, 6
471#define ICC_IGRPEN1 p15, 0, c12, c12, 7
472#define ICC_MGRPEN1 p15, 6, c12, c12, 7
473
474/* 64 bit system register defines The format is: coproc, opt1, CRm */
475#define TTBR0_64 p15, 0, c2
476#define TTBR1_64 p15, 1, c2
477#define CNTVOFF_64 p15, 4, c14
478#define VTTBR_64 p15, 6, c2
479#define CNTPCT_64 p15, 0, c14
480
481/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
482#define ICC_SGI1R_EL1_64 p15, 0, c12
483#define ICC_ASGI1R_EL1_64 p15, 1, c12
484#define ICC_SGI0R_EL1_64 p15, 2, c12
485
Isla Mitchell02c63072017-07-21 14:44:36 +0100486/*******************************************************************************
487 * Definitions of MAIR encodings for device and normal memory
488 ******************************************************************************/
489/*
490 * MAIR encodings for device memory attributes.
491 */
492#define MAIR_DEV_nGnRnE U(0x0)
493#define MAIR_DEV_nGnRE U(0x4)
494#define MAIR_DEV_nGRE U(0x8)
495#define MAIR_DEV_GRE U(0xc)
496
497/*
498 * MAIR encodings for normal memory attributes.
499 *
500 * Cache Policy
501 * WT: Write Through
502 * WB: Write Back
503 * NC: Non-Cacheable
504 *
505 * Transient Hint
506 * NTR: Non-Transient
507 * TR: Transient
508 *
509 * Allocation Policy
510 * RA: Read Allocate
511 * WA: Write Allocate
512 * RWA: Read and Write Allocate
513 * NA: No Allocation
514 */
515#define MAIR_NORM_WT_TR_WA U(0x1)
516#define MAIR_NORM_WT_TR_RA U(0x2)
517#define MAIR_NORM_WT_TR_RWA U(0x3)
518#define MAIR_NORM_NC U(0x4)
519#define MAIR_NORM_WB_TR_WA U(0x5)
520#define MAIR_NORM_WB_TR_RA U(0x6)
521#define MAIR_NORM_WB_TR_RWA U(0x7)
522#define MAIR_NORM_WT_NTR_NA U(0x8)
523#define MAIR_NORM_WT_NTR_WA U(0x9)
524#define MAIR_NORM_WT_NTR_RA U(0xa)
525#define MAIR_NORM_WT_NTR_RWA U(0xb)
526#define MAIR_NORM_WB_NTR_NA U(0xc)
527#define MAIR_NORM_WB_NTR_WA U(0xd)
528#define MAIR_NORM_WB_NTR_RA U(0xe)
529#define MAIR_NORM_WB_NTR_RWA U(0xf)
530
531#define MAIR_NORM_OUTER_SHIFT 4
532
533#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
534
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100535/*******************************************************************************
536 * Definitions for system register interface to AMU for ARMv8.4 onwards
537 ******************************************************************************/
538#define AMCR p15, 0, c13, c2, 0
539#define AMCFGR p15, 0, c13, c2, 1
540#define AMCGCR p15, 0, c13, c2, 2
541#define AMUSERENR p15, 0, c13, c2, 3
542#define AMCNTENCLR0 p15, 0, c13, c2, 4
543#define AMCNTENSET0 p15, 0, c13, c2, 5
544#define AMCNTENCLR1 p15, 0, c13, c3, 0
545#define AMCNTENSET1 p15, 0, c13, c1, 1
546
547/* Activity Monitor Group 0 Event Counter Registers */
548#define AMEVCNTR00 p15, 0, c0
549#define AMEVCNTR01 p15, 1, c0
550#define AMEVCNTR02 p15, 2, c0
551#define AMEVCNTR03 p15, 3, c0
552
553/* Activity Monitor Group 0 Event Type Registers */
554#define AMEVTYPER00 p15, 0, c13, c6, 0
555#define AMEVTYPER01 p15, 0, c13, c6, 1
556#define AMEVTYPER02 p15, 0, c13, c6, 2
557#define AMEVTYPER03 p15, 0, c13, c6, 3
558
Soby Mathewc6820d12016-05-09 17:49:55 +0100559#endif /* __ARCH_H__ */