| Nicolas Le Bayon | cc3f108 | 2019-05-22 19:20:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2024, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef BSEC3_REG_H |
| 8 | #define BSEC3_REG_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /* BSEC REGISTER OFFSET (base relative) */ |
| 13 | #define BSEC_FVR(x) (U(0x000) + 4U * (x)) |
| 14 | #define BSEC_SPLOCK(x) (U(0x800) + 4U * (x)) |
| 15 | #define BSEC_SWLOCK(x) (U(0x840) + 4U * (x)) |
| 16 | #define BSEC_SRLOCK(x) (U(0x880) + 4U * (x)) |
| 17 | #define BSEC_OTPVLDR(x) (U(0x8C0) + 4U * (x)) |
| 18 | #define BSEC_SFSR(x) (U(0x940) + 4U * (x)) |
| 19 | #define BSEC_OTPCR U(0xC04) |
| 20 | #define BSEC_WDR U(0xC08) |
| 21 | #define BSEC_SCRATCHR0 U(0xE00) |
| 22 | #define BSEC_SCRATCHR1 U(0xE04) |
| 23 | #define BSEC_SCRATCHR2 U(0xE08) |
| 24 | #define BSEC_SCRATCHR3 U(0xE0C) |
| 25 | #define BSEC_LOCKR U(0xE10) |
| 26 | #define BSEC_JTAGINR U(0xE14) |
| 27 | #define BSEC_JTAGOUTR U(0xE18) |
| 28 | #define BSEC_DENR U(0xE20) |
| 29 | #define BSEC_UNMAPR U(0xE24) |
| 30 | #define BSEC_SR U(0xE40) |
| 31 | #define BSEC_OTPSR U(0xE44) |
| 32 | #define BSEC_WRCR U(0xF00) |
| 33 | #define BSEC_HWCFGR U(0xFF0) |
| 34 | #define BSEC_VERR U(0xFF4) |
| 35 | #define BSEC_IPIDR U(0xFF8) |
| 36 | #define BSEC_SIDR U(0xFFC) |
| 37 | |
| 38 | /* BSEC_OTPCR register fields */ |
| 39 | #define BSEC_OTPCR_ADDR_MASK GENMASK_32(8, 0) |
| 40 | #define BSEC_OTPCR_ADDR_SHIFT U(0) |
| 41 | #define BSEC_OTPCR_PROG BIT_32(13) |
| 42 | #define BSEC_OTPCR_PPLOCK BIT_32(14) |
| 43 | #define BSEC_OTPCR_LASTCID_MASK GENMASK_32(21, 19) |
| 44 | #define BSEC_OTPCR_LASTCID_SHIFT U(19) |
| 45 | |
| 46 | /* BSEC_LOCKR register fields */ |
| 47 | #define BSEC_LOCKR_GWLOCK_MASK BIT_32(0) |
| 48 | #define BSEC_LOCKR_GWLOCK_SHIFT U(0) |
| 49 | #define BSEC_LOCKR_DENLOCK_MASK BIT_32(1) |
| 50 | #define BSEC_LOCKR_DENLOCK_SHIFT U(1) |
| 51 | #define BSEC_LOCKR_HKLOCK_MASK BIT_32(2) |
| 52 | #define BSEC_LOCKR_HKLOCK_SHIFT U(2) |
| 53 | |
| 54 | /* BSEC_DENR register fields */ |
| 55 | #define BSEC_DENR_LPDBGEN BIT_32(0) |
| 56 | #define BSEC_DENR_DBGENA BIT_32(1) |
| 57 | #define BSEC_DENR_NIDENA BIT_32(2) |
| 58 | #define BSEC_DENR_DEVICEEN BIT_32(3) |
| 59 | #define BSEC_DENR_HDPEN BIT_32(4) |
| 60 | #define BSEC_DENR_SPIDENA BIT_32(5) |
| 61 | #define BSEC_DENR_SPNIDENA BIT_32(6) |
| 62 | #define BSEC_DENR_DBGSWEN BIT_32(7) |
| 63 | #define BSEC_DENR_DBGENM BIT_32(8) |
| 64 | #define BSEC_DENR_NIDENM BIT_32(9) |
| 65 | #define BSEC_DENR_SPIDENM BIT_32(10) |
| 66 | #define BSEC_DENR_SPNIDENM BIT_32(11) |
| 67 | #define BSEC_DENR_CFGSDIS BIT_32(12) |
| 68 | #define BSEC_DENR_CP15SDIS_MASK GENMASK_32(14, 13) |
| 69 | #define BSEC_DENR_CP15SDIS_SHIFT U(13) |
| 70 | #define BSEC_DENR_LPDBGDIS BIT_32(15) |
| 71 | #define BSEC_DENR_ALL_MSK GENMASK_32(15, 0) |
| 72 | |
| 73 | /* BSEC_SR register fields */ |
| 74 | #define BSEC_SR_BUSY BIT_32(0) |
| 75 | #define BSEC_SR_HVALID BIT_32(1) |
| 76 | #define BSEC_SR_RNGERR BIT_32(2) |
| 77 | #define BSEC_SR_HKWW_MASK GENMASK_32(15, 8) |
| 78 | #define BSEC_SR_HKWW_SHIFT U(8) |
| 79 | #define BSEC_SR_NVSTATE_MASK GENMASK_32(31, 26) |
| 80 | #define BSEC_SR_NVSTATE_SHIFT U(26) |
| 81 | #define BSEC_SR_NVSTATE_OPEN U(0x16) |
| 82 | #define BSEC_SR_NVSTATE_CLOSED U(0x0D) |
| 83 | #define BSEC_SR_NVSTATE_OTP_LOCKED U(0x23) |
| 84 | |
| 85 | /* BSEC_OTPSR register fields */ |
| 86 | #define BSEC_OTPSR_BUSY BIT_32(0) |
| 87 | #define BSEC_OTPSR_FUSEOK BIT_32(1) |
| 88 | #define BSEC_OTPSR_HIDEUP BIT_32(2) |
| 89 | #define BSEC_OTPSR_OTPNVIR BIT_32(4) |
| 90 | #define BSEC_OTPSR_OTPERR BIT_32(5) |
| 91 | #define BSEC_OTPSR_OTPSEC BIT_32(6) |
| 92 | #define BSEC_OTPSR_PROGFAIL BIT_32(16) |
| 93 | #define BSEC_OTPSR_DISTURBF BIT_32(17) |
| 94 | #define BSEC_OTPSR_DEDF BIT_32(18) |
| 95 | #define BSEC_OTPSR_SECF BIT_32(19) |
| 96 | #define BSEC_OTPSR_PPLF BIT_32(20) |
| 97 | #define BSEC_OTPSR_PPLMF BIT_32(21) |
| 98 | #define BSEC_OTPSR_AMEF BIT_32(22) |
| 99 | |
| 100 | /* BSEC_VERR register fields */ |
| 101 | #define BSEC_VERR_MASK GENMASK_32(7, 0) |
| 102 | |
| 103 | #endif /* BSEC3_REG_H */ |