blob: 0d076b49102c5410d497a89521361b241e2cc184 [file] [log] [blame]
Roberto Vargase92111a2018-05-22 16:05:42 +01001/*
Govindraj Rajaeee28e72023-08-01 15:52:40 -05002 * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
Roberto Vargase92111a2018-05-22 16:05:42 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <lib/xlat_tables/xlat_tables_defs.h>
Roberto Vargase92111a2018-05-22 16:05:42 +01008#include <platform_def.h>
Roberto Vargase92111a2018-05-22 16:05:42 +01009
10MEMORY {
Chris Kay4b7660a2022-09-29 14:36:53 +010011 ROM (rx): ORIGIN = ROMLIB_RO_BASE, LENGTH = ROMLIB_RO_LIMIT - ROMLIB_RO_BASE
12 RAM (rwx): ORIGIN = ROMLIB_RW_BASE, LENGTH = ROMLIB_RW_END - ROMLIB_RW_BASE
Roberto Vargase92111a2018-05-22 16:05:42 +010013}
14
15OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
16OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
17ENTRY(jmptbl)
18
Chris Kay4b7660a2022-09-29 14:36:53 +010019SECTIONS {
20 . = ROMLIB_RO_BASE;
Roberto Vargase92111a2018-05-22 16:05:42 +010021
Chris Kay4b7660a2022-09-29 14:36:53 +010022 .text : {
23 *jmptbl.o(.text)
24 *(.text*)
25 *(.rodata*)
26 } >ROM
Roberto Vargase92111a2018-05-22 16:05:42 +010027
Chris Kay4b7660a2022-09-29 14:36:53 +010028 __DATA_ROM_START__ = LOADADDR(.data);
Roberto Vargase92111a2018-05-22 16:05:42 +010029
Chris Kay4b7660a2022-09-29 14:36:53 +010030 .data : {
31 __DATA_RAM_START__ = .;
32
33 *(.data*)
34
35 __DATA_RAM_END__ = .;
36 } >RAM AT>ROM
37
38 __DATA_SIZE__ = SIZEOF(.data);
39
40 .bss : {
41 __BSS_START__ = .;
42
43 *(.bss*)
44
45 __BSS_END__ = .;
46 } >RAM
Roberto Vargase92111a2018-05-22 16:05:42 +010047
Chris Kay4b7660a2022-09-29 14:36:53 +010048 __BSS_SIZE__ = SIZEOF(.bss);
Roberto Vargase92111a2018-05-22 16:05:42 +010049}