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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley9df48042015-03-19 18:58:55 +000031#include <arch_helpers.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010032#include <assert.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010033#include <cassert.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010034#include <css_pm.h>
Dan Handley9df48042015-03-19 18:58:55 +000035#include <debug.h>
36#include <errno.h>
37#include <plat_arm.h>
38#include <platform.h>
39#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000040#include "css_scpi.h"
41
Soby Mathew12012dd2015-10-26 14:01:53 +000042/* Macros to read the CSS power domain state */
43#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
44#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
45#define CSS_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > ARM_PWR_LVL1) ?\
46 (state)->pwr_domain_state[ARM_PWR_LVL2] : 0)
47
Soby Mathewfeac8fc2015-09-29 15:47:16 +010048/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
49#pragma weak plat_arm_psci_pm_ops
Soby Mathewfec4eb72015-07-01 16:16:20 +010050
Soby Mathew7799cf72015-04-16 14:49:09 +010051#if ARM_RECOM_STATE_ID_ENC
52/*
53 * The table storing the valid idle power states. Ensure that the
54 * array entries are populated in ascending order of state-id to
55 * enable us to use binary search during power state validation.
56 * The table must be terminated by a NULL entry.
57 */
58const unsigned int arm_pm_idle_states[] = {
Soby Mathewa869de12015-05-08 10:18:59 +010059 /* State-id - 0x001 */
60 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
61 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
62 /* State-id - 0x002 */
63 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
64 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
65 /* State-id - 0x022 */
66 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
67 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
68#if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
69 /* State-id - 0x222 */
70 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
71 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
72#endif
Soby Mathew7799cf72015-04-16 14:49:09 +010073 0,
74};
Soby Mathewa869de12015-05-08 10:18:59 +010075#endif /* __ARM_RECOM_STATE_ID_ENC__ */
Soby Mathew7799cf72015-04-16 14:49:09 +010076
Soby Mathew61e8d0b2015-10-12 17:32:29 +010077/*
78 * All the power management helpers in this file assume at least cluster power
79 * level is supported.
80 */
81CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
82 assert_max_pwr_lvl_supported_mismatch);
83
Dan Handley9df48042015-03-19 18:58:55 +000084/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010085 * Handler called when a power domain is about to be turned on. The
Dan Handley9df48042015-03-19 18:58:55 +000086 * level and mpidr determine the affinity instance.
87 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010088int css_pwr_domain_on(u_register_t mpidr)
Dan Handley9df48042015-03-19 18:58:55 +000089{
90 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +010091 * SCP takes care of powering up parent power domains so we
Dan Handley9df48042015-03-19 18:58:55 +000092 * only need to care about level 0
93 */
Dan Handley9df48042015-03-19 18:58:55 +000094 scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on,
95 scpi_power_on);
96
97 return PSCI_E_SUCCESS;
98}
99
Soby Mathew12012dd2015-10-26 14:01:53 +0000100static void css_pwr_domain_on_finisher_common(
101 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000102{
Soby Mathew12012dd2015-10-26 14:01:53 +0000103 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100104
Dan Handley9df48042015-03-19 18:58:55 +0000105 /*
106 * Perform the common cluster specific operations i.e enable coherency
107 * if this cluster was off.
108 */
Soby Mathew12012dd2015-10-26 14:01:53 +0000109 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000110 plat_arm_interconnect_enter_coherency();
Soby Mathew12012dd2015-10-26 14:01:53 +0000111}
Dan Handley9df48042015-03-19 18:58:55 +0000112
Soby Mathew12012dd2015-10-26 14:01:53 +0000113/*******************************************************************************
114 * Handler called when a power level has just been powered on after
115 * being turned off earlier. The target_state encodes the low power state that
116 * each level has woken up from. This handler would never be invoked with
117 * the system power domain uninitialized as either the primary would have taken
118 * care of it as part of cold boot or the first core awakened from system
119 * suspend would have already initialized it.
120 ******************************************************************************/
121void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
122{
123 /* Assert that the system power domain need not be initialized */
124 assert(CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_RUN);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100125
Soby Mathew12012dd2015-10-26 14:01:53 +0000126 css_pwr_domain_on_finisher_common(target_state);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100127
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000128 /* Program the gic per-cpu distributor or re-distributor interface */
129 plat_arm_gic_pcpu_init();
130
Dan Handley9df48042015-03-19 18:58:55 +0000131 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000132 plat_arm_gic_cpuif_enable();
Dan Handley9df48042015-03-19 18:58:55 +0000133}
134
135/*******************************************************************************
136 * Common function called while turning a cpu off or suspending it. It is called
137 * from css_off() or css_suspend() when these functions in turn are called for
Soby Mathewfec4eb72015-07-01 16:16:20 +0100138 * power domain at the highest power level which will be powered down. It
139 * performs the actions common to the OFF and SUSPEND calls.
Dan Handley9df48042015-03-19 18:58:55 +0000140 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100141static void css_power_down_common(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000142{
143 uint32_t cluster_state = scpi_power_on;
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100144 uint32_t system_state = scpi_power_on;
Dan Handley9df48042015-03-19 18:58:55 +0000145
146 /* Prevent interrupts from spuriously waking up this cpu */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000147 plat_arm_gic_cpuif_disable();
Dan Handley9df48042015-03-19 18:58:55 +0000148
Soby Mathew12012dd2015-10-26 14:01:53 +0000149 /* Check if power down at system power domain level is requested */
150 if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100151 system_state = scpi_power_retention;
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100152
Dan Handley9df48042015-03-19 18:58:55 +0000153 /* Cluster is to be turned off, so disable coherency */
Soby Mathew12012dd2015-10-26 14:01:53 +0000154 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000155 plat_arm_interconnect_exit_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000156 cluster_state = scpi_power_off;
157 }
158
159 /*
160 * Ask the SCP to power down the appropriate components depending upon
161 * their state.
162 */
163 scpi_set_css_power_state(read_mpidr_el1(),
164 scpi_power_off,
165 cluster_state,
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100166 system_state);
Dan Handley9df48042015-03-19 18:58:55 +0000167}
168
169/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100170 * Handler called when a power domain is about to be turned off. The
171 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000172 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100173void css_pwr_domain_off(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000174{
Soby Mathew12012dd2015-10-26 14:01:53 +0000175 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100176 css_power_down_common(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000177}
178
179/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100180 * Handler called when a power domain is about to be suspended. The
181 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000182 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100183void css_pwr_domain_suspend(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000184{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100185 /*
Soby Mathew12012dd2015-10-26 14:01:53 +0000186 * CSS currently supports retention only at cpu level. Just return
Soby Mathewfec4eb72015-07-01 16:16:20 +0100187 * as nothing is to be done for retention.
188 */
Soby Mathew12012dd2015-10-26 14:01:53 +0000189 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Dan Handley9df48042015-03-19 18:58:55 +0000190 return;
191
Soby Mathew12012dd2015-10-26 14:01:53 +0000192 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100193 css_power_down_common(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000194}
195
196/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100197 * Handler called when a power domain has just been powered on after
198 * having been suspended earlier. The target_state encodes the low power state
199 * that each level has woken up from.
Dan Handley9df48042015-03-19 18:58:55 +0000200 * TODO: At the moment we reuse the on finisher and reinitialize the secure
201 * context. Need to implement a separate suspend finisher.
202 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100203void css_pwr_domain_suspend_finish(
Soby Mathewfec4eb72015-07-01 16:16:20 +0100204 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000205{
Soby Mathew12012dd2015-10-26 14:01:53 +0000206 /* Return as nothing is to be done on waking up from retention. */
207 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Soby Mathewfec4eb72015-07-01 16:16:20 +0100208 return;
209
Soby Mathew12012dd2015-10-26 14:01:53 +0000210 /* Perform system domain restore if woken up from system suspend */
211 if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
212 arm_system_pwr_domain_resume();
213 else
214 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000215 plat_arm_gic_cpuif_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +0000216
217 css_pwr_domain_on_finisher_common(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000218}
219
220/*******************************************************************************
221 * Handlers to shutdown/reboot the system
222 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100223void __dead2 css_system_off(void)
Dan Handley9df48042015-03-19 18:58:55 +0000224{
225 uint32_t response;
226
227 /* Send the power down request to the SCP */
228 response = scpi_sys_power_state(scpi_system_shutdown);
229
230 if (response != SCP_OK) {
231 ERROR("CSS System Off: SCP error %u.\n", response);
232 panic();
233 }
234 wfi();
235 ERROR("CSS System Off: operation not handled.\n");
236 panic();
237}
238
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100239void __dead2 css_system_reset(void)
Dan Handley9df48042015-03-19 18:58:55 +0000240{
241 uint32_t response;
242
243 /* Send the system reset request to the SCP */
244 response = scpi_sys_power_state(scpi_system_reboot);
245
246 if (response != SCP_OK) {
247 ERROR("CSS System Reset: SCP error %u.\n", response);
248 panic();
249 }
250 wfi();
251 ERROR("CSS System Reset: operation not handled.\n");
252 panic();
253}
254
255/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100256 * Handler called when the CPU power domain is about to enter standby.
Dan Handley9df48042015-03-19 18:58:55 +0000257 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100258void css_cpu_standby(plat_local_state_t cpu_state)
Dan Handley9df48042015-03-19 18:58:55 +0000259{
260 unsigned int scr;
261
Soby Mathewfec4eb72015-07-01 16:16:20 +0100262 assert(cpu_state == ARM_LOCAL_STATE_RET);
263
Dan Handley9df48042015-03-19 18:58:55 +0000264 scr = read_scr_el3();
David Wangc1d9cfb2016-06-07 09:22:40 +0800265 /*
266 * Enable the Non secure interrupt to wake the CPU.
267 * In GICv3 affinity routing mode, the non secure group1 interrupts use
268 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ.
269 * Enabling both the bits works for both GICv2 mode and GICv3 affinity
270 * routing mode.
271 */
272 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
Dan Handley9df48042015-03-19 18:58:55 +0000273 isb();
274 dsb();
275 wfi();
276
277 /*
278 * Restore SCR to the original value, synchronisation of scr_el3 is
279 * done by eret while el3_exit to save some execution cycles.
280 */
281 write_scr_el3(scr);
282}
283
284/*******************************************************************************
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100285 * Handler called to return the 'req_state' for system suspend.
286 ******************************************************************************/
287void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
288{
289 unsigned int i;
290
291 /*
292 * System Suspend is supported only if the system power domain node
293 * is implemented.
294 */
295 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
296
297 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
298 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
299}
300
301/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100302 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
303 * platform will take care of registering the handlers with PSCI.
Dan Handley9df48042015-03-19 18:58:55 +0000304 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100305const plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100306 .pwr_domain_on = css_pwr_domain_on,
307 .pwr_domain_on_finish = css_pwr_domain_on_finish,
308 .pwr_domain_off = css_pwr_domain_off,
309 .cpu_standby = css_cpu_standby,
310 .pwr_domain_suspend = css_pwr_domain_suspend,
311 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish,
Dan Handley9df48042015-03-19 18:58:55 +0000312 .system_off = css_system_off,
313 .system_reset = css_system_reset,
Soby Mathew0d9e8522015-07-15 13:36:24 +0100314 .validate_power_state = arm_validate_power_state,
315 .validate_ns_entrypoint = arm_validate_ns_entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000316};