Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 1 | /* |
Ronak Jain | 325bad1 | 2021-12-21 01:39:59 -0800 | [diff] [blame] | 2 | * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * ZynqMP system level PM-API functions for pin control. |
| 9 | */ |
| 10 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 11 | #ifndef PM_API_IOCTL_H |
| 12 | #define PM_API_IOCTL_H |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 13 | |
| 14 | #include "pm_common.h" |
| 15 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 16 | //ioctl id |
| 17 | enum { |
Ronak Jain | 26a8bb2 | 2021-06-27 22:31:20 -0700 | [diff] [blame] | 18 | IOCTL_GET_RPU_OPER_MODE = 0, |
| 19 | IOCTL_SET_RPU_OPER_MODE = 1, |
| 20 | IOCTL_RPU_BOOT_ADDR_CONFIG = 2, |
| 21 | IOCTL_TCM_COMB_CONFIG = 3, |
| 22 | IOCTL_SET_TAPDELAY_BYPASS = 4, |
| 23 | IOCTL_SET_SGMII_MODE = 5, |
| 24 | IOCTL_SD_DLL_RESET = 6, |
| 25 | IOCTL_SET_SD_TAPDELAY = 7, |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 26 | /* Ioctl for clock driver */ |
Ronak Jain | 26a8bb2 | 2021-06-27 22:31:20 -0700 | [diff] [blame] | 27 | IOCTL_SET_PLL_FRAC_MODE = 8, |
| 28 | IOCTL_GET_PLL_FRAC_MODE = 9, |
| 29 | IOCTL_SET_PLL_FRAC_DATA = 10, |
| 30 | IOCTL_GET_PLL_FRAC_DATA = 11, |
| 31 | IOCTL_WRITE_GGS = 12, |
| 32 | IOCTL_READ_GGS = 13, |
| 33 | IOCTL_WRITE_PGGS = 14, |
| 34 | IOCTL_READ_PGGS = 15, |
Siva Durga Prasad Paladugu | ed1d5cb | 2018-09-04 17:03:25 +0530 | [diff] [blame] | 35 | /* IOCTL for ULPI reset */ |
Ronak Jain | 26a8bb2 | 2021-06-27 22:31:20 -0700 | [diff] [blame] | 36 | IOCTL_ULPI_RESET = 16, |
Siva Durga Prasad Paladugu | ac8526f | 2018-09-04 17:12:51 +0530 | [diff] [blame] | 37 | /* Set healthy bit value */ |
Ronak Jain | 26a8bb2 | 2021-06-27 22:31:20 -0700 | [diff] [blame] | 38 | IOCTL_SET_BOOT_HEALTH_STATUS = 17, |
| 39 | IOCTL_AFI = 18, |
| 40 | /* Probe counter read/write */ |
| 41 | IOCTL_PROBE_COUNTER_READ = 19, |
| 42 | IOCTL_PROBE_COUNTER_WRITE = 20, |
| 43 | IOCTL_OSPI_MUX_SELECT = 21, |
| 44 | /* IOCTL for USB power request */ |
| 45 | IOCTL_USB_SET_STATE = 22, |
| 46 | /* IOCTL to get last reset reason */ |
| 47 | IOCTL_GET_LAST_RESET_REASON = 23, |
| 48 | /* AI engine NPI ISR clear */ |
| 49 | IOCTL_AIE_ISR_CLEAR = 24, |
| 50 | /* Register SGI to ATF */ |
| 51 | IOCTL_REGISTER_SGI = 25, |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 52 | }; |
| 53 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 54 | //RPU operation mode |
| 55 | #define PM_RPU_MODE_LOCKSTEP 0U |
| 56 | #define PM_RPU_MODE_SPLIT 1U |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 57 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 58 | //RPU boot mem |
| 59 | #define PM_RPU_BOOTMEM_LOVEC 0U |
| 60 | #define PM_RPU_BOOTMEM_HIVEC 1U |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 61 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 62 | //RPU tcm mpde |
| 63 | #define PM_RPU_TCM_SPLIT 0U |
| 64 | #define PM_RPU_TCM_COMB 1U |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 65 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 66 | //tap delay signal type |
| 67 | #define PM_TAPDELAY_NAND_DQS_IN 0U |
| 68 | #define PM_TAPDELAY_NAND_DQS_OUT 1U |
| 69 | #define PM_TAPDELAY_QSPI 2U |
| 70 | #define PM_TAPDELAY_MAX 3U |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 71 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 72 | //tap delay bypass |
| 73 | #define PM_TAPDELAY_BYPASS_DISABLE 0U |
| 74 | #define PM_TAPDELAY_BYPASS_ENABLE 1U |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 75 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 76 | //sgmii mode |
| 77 | #define PM_SGMII_DISABLE 0U |
| 78 | #define PM_SGMII_ENABLE 1U |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 79 | |
| 80 | enum tap_delay_type { |
| 81 | PM_TAPDELAY_INPUT, |
| 82 | PM_TAPDELAY_OUTPUT, |
| 83 | }; |
| 84 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 85 | //dll reset type |
| 86 | #define PM_DLL_RESET_ASSERT 0U |
| 87 | #define PM_DLL_RESET_RELEASE 1U |
| 88 | #define PM_DLL_RESET_PULSE 2U |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 89 | |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 90 | enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 91 | uint32_t ioctl_id, |
| 92 | uint32_t arg1, |
| 93 | uint32_t arg2, |
| 94 | uint32_t *value); |
Ronak Jain | 325bad1 | 2021-12-21 01:39:59 -0800 | [diff] [blame] | 95 | enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask); |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 96 | #endif /* PM_API_IOCTL_H */ |