blob: b3559b20f6681cdd9abbe91032e9fde7c66fd8a8 [file] [log] [blame]
Lin Huang30e43392017-05-04 16:02:45 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#ifndef __ROCKCHIP_PLAT_LD_S__
7#define __ROCKCHIP_PLAT_LD_S__
8
9MEMORY {
10 PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
11}
12
13SECTIONS
14{
15 . = PMUSRAM_BASE;
16
17 /*
18 * pmu_cpuson_entrypoint request address
19 * align 64K when resume, so put it in the
20 * start of pmusram
21 */
22 .text_pmusram : {
23 ASSERT(. == ALIGN(64 * 1024),
24 ".pmusram.entry request 64K aligned.");
25 *(.pmusram.entry)
26 __bl31_pmusram_text_start = .;
27 *(.pmusram.text)
28 *(.pmusram.rodata)
29 __bl31_pmusram_text_end = .;
30 __bl31_pmusram_data_start = .;
31 *(.pmusram.data)
32 __bl31_pmusram_data_end = .;
33
34 } >PMUSRAM
35}
36
37#endif /* __ROCKCHIP_PLAT_LD_S__ */