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Marcin Juszkiewicz7754e822023-07-24 20:56:29 +02001#
Jean-Philippe Brucker6125ee42023-09-06 16:18:02 +01002# Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
Marcin Juszkiewicz7754e822023-07-24 20:56:29 +02003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/libfdt/libfdt.mk
8include common/fdt_wrappers.mk
9
Marcin Juszkiewicza70ef5e2023-07-24 21:08:16 +020010PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
11 -I${PLAT_QEMU_COMMON_PATH}/include \
12 -I${PLAT_QEMU_PATH}/include \
13 -Iinclude/common/tbbr
14
15ifeq (${ARCH},aarch32)
16QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
17else
18QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
19 lib/cpus/aarch64/cortex_a53.S \
developer618fd512023-09-13 19:50:24 +080020 lib/cpus/aarch64/cortex_a55.S \
Marcin Juszkiewicza70ef5e2023-07-24 21:08:16 +020021 lib/cpus/aarch64/cortex_a57.S \
22 lib/cpus/aarch64/cortex_a72.S \
23 lib/cpus/aarch64/cortex_a76.S \
Marcin Juszkiewicz4b5a2c22023-09-12 13:08:13 +020024 lib/cpus/aarch64/cortex_a710.S \
Marcin Juszkiewicza70ef5e2023-07-24 21:08:16 +020025 lib/cpus/aarch64/neoverse_n_common.S \
26 lib/cpus/aarch64/neoverse_n1.S \
27 lib/cpus/aarch64/neoverse_v1.S \
Marcin Juszkiewiczc36f42b2023-09-15 22:44:04 +020028 lib/cpus/aarch64/neoverse_n2.S \
Marcin Juszkiewicza70ef5e2023-07-24 21:08:16 +020029 lib/cpus/aarch64/qemu_max.S
30
31PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
32endif
Marcin Juszkiewicz424e3a82023-07-24 21:18:51 +020033
34PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
35 ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
36 drivers/arm/pl011/${ARCH}/pl011_console.S
37
38include lib/xlat_tables_v2/xlat_tables.mk
39PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
40
41ifneq ($(ENABLE_STACK_PROTECTOR), 0)
42 PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
43endif
44
45BL1_SOURCES += drivers/io/io_semihosting.c \
46 drivers/io/io_storage.c \
47 drivers/io/io_fip.c \
48 drivers/io/io_memmap.c \
49 lib/semihosting/semihosting.c \
50 lib/semihosting/${ARCH}/semihosting_call.S \
51 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
52 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
53 ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
54 ${QEMU_CPU_LIBS}
55
56BL2_SOURCES += drivers/io/io_semihosting.c \
57 drivers/io/io_storage.c \
58 drivers/io/io_fip.c \
59 drivers/io/io_memmap.c \
60 lib/semihosting/semihosting.c \
61 lib/semihosting/${ARCH}/semihosting_call.S \
62 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
63 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
64 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
65 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
66 ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
67 common/desc_image_load.c \
Mathieu Poirier9c84fe22024-10-31 09:46:25 -060068 common/fdt_fixup.c \
69 ${FDT_WRAPPERS_SOURCES}
Marcin Juszkiewicz61c99032023-07-24 21:37:00 +020070
71BL31_SOURCES += ${QEMU_CPU_LIBS} \
72 lib/semihosting/semihosting.c \
73 lib/semihosting/${ARCH}/semihosting_call.S \
74 plat/common/plat_psci_common.c \
75 ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
76 ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
77 common/fdt_fixup.c \
78 ${QEMU_GIC_SOURCES}
79
Marcin Juszkiewicz8acc2da2023-07-24 21:44:17 +020080# CPU flag enablement
Marcin Juszkiewicz5aece712023-07-24 22:07:49 +020081ifeq (${ARCH},aarch64)
Marcin Juszkiewicz8acc2da2023-07-24 21:44:17 +020082
Marcin Juszkiewiczc4dae6e2023-11-13 16:18:49 +010083# Cpu core architecture level:
84# v8.0: a53, a57, a72
85# v8.2: a55, a76, n1
86# v8.4: v1
87# v9.0: a710, n2
88#
89#
90# We go v8.0 by default and will enable all features we want
91
Jean-Philippe Brucker2a82ca62024-04-16 16:23:46 +010092ARM_ARCH_MAJOR ?= 8
93ARM_ARCH_MINOR ?= 0
Marcin Juszkiewiczc4dae6e2023-11-13 16:18:49 +010094
95# 8.0
96ENABLE_FEAT_CSV2_2 := 2
97
98# 8.1
99ENABLE_FEAT_PAN := 2
100ENABLE_FEAT_VHE := 2
101
102# 8.2
103# TF-A currently does not permit dynamic detection of FEAT_RAS
104# so this is the only safe setting
105ENABLE_FEAT_RAS := 0
106
107# 8.4
108ENABLE_FEAT_SEL2 := 2
109ENABLE_FEAT_DIT := 2
Jean-Philippe Brucker2a82ca62024-04-16 16:23:46 +0100110ENABLE_TRF_FOR_NS := 2
Marcin Juszkiewiczc4dae6e2023-11-13 16:18:49 +0100111
112# 8.5
113ENABLE_FEAT_RNG := 2
Marcin Juszkiewicz69ae7da2024-02-08 12:07:45 +0100114# TF-A currently does not do dynamic detection of FEAT_SB.
115# Compiler puts SB instruction when it is enabled.
116ENABLE_FEAT_SB := 0
Marcin Juszkiewiczc4dae6e2023-11-13 16:18:49 +0100117
118# 8.6
Jean-Philippe Bruckerbeaccd12024-04-15 14:28:11 +0100119ENABLE_FEAT_ECV := 2
Marcin Juszkiewiczc4dae6e2023-11-13 16:18:49 +0100120ENABLE_FEAT_FGT := 2
121
122# 8.7
123ENABLE_FEAT_HCX := 2
124
Marcin Juszkiewicz5aece712023-07-24 22:07:49 +0200125# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks)
126ifeq (${SPM_MM},1)
127 ENABLE_SVE_FOR_NS := 0
128 ENABLE_SME_FOR_NS := 0
129else
Marcin Juszkiewicz8acc2da2023-07-24 21:44:17 +0200130 ENABLE_SVE_FOR_NS := 2
131 ENABLE_SME_FOR_NS := 2
132endif
133
Jean-Philippe Brucker6125ee42023-09-06 16:18:02 +0100134ifeq (${ENABLE_RME},1)
135BL31_SOURCES += plat/qemu/common/qemu_plat_attest_token.c \
136 plat/qemu/common/qemu_realm_attest_key.c
137endif
138
Marcin Juszkiewicz676443b2023-07-24 21:54:34 +0200139# Treating this as a memory-constrained port for now
140USE_COHERENT_MEM := 0
141
142# This can be overridden depending on CPU(s) used in the QEMU image
143HW_ASSISTED_COHERENCY := 1
144
145CTX_INCLUDE_AARCH32_REGS := 0
146ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
147$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
148endif
Marcin Juszkiewicz1da28d12023-08-21 21:17:12 +0200149
150# Pointer Authentication sources
151ifeq (${ENABLE_PAUTH}, 1)
152PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
153CTX_INCLUDE_PAUTH_REGS := 1
154endif
155
Marcin Juszkiewicz676443b2023-07-24 21:54:34 +0200156endif