Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 1 | /* |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 2 | * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | |
| 9 | #include <bl32/sp_min/platform_sp_min.h> |
| 10 | #include <common/debug.h> |
| 11 | #include <lib/fconf/fconf.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 12 | #include <plat/arm/common/plat_arm.h> |
| 13 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 14 | #include "../fvp_private.h" |
| 15 | |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 16 | uintptr_t hw_config_dtb; |
| 17 | |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 18 | void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 19 | u_register_t arg2, u_register_t arg3) |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 20 | { |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 21 | arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 22 | |
| 23 | /* Initialize the platform config for future decision making */ |
| 24 | fvp_config_setup(); |
| 25 | |
| 26 | /* |
| 27 | * Initialize the correct interconnect for this cluster during cold |
| 28 | * boot. No need for locks as no other CPU is active. |
| 29 | */ |
| 30 | fvp_interconnect_init(); |
| 31 | |
| 32 | /* |
| 33 | * Enable coherency in interconnect for the primary CPU's cluster. |
| 34 | * Earlier bootloader stages might already do this (e.g. Trusted |
| 35 | * Firmware's BL1 does it) but we can't assume so. There is no harm in |
| 36 | * executing this code twice anyway. |
| 37 | * FVP PSCI code will enable coherency for other clusters. |
| 38 | */ |
| 39 | fvp_interconnect_enable(); |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 40 | |
| 41 | hw_config_dtb = arg2; |
| 42 | } |
| 43 | |
| 44 | void sp_min_plat_arch_setup(void) |
| 45 | { |
| 46 | arm_sp_min_plat_arch_setup(); |
| 47 | |
| 48 | /* |
| 49 | * For RESET_TO_SP_MIN systems, SP_MIN(BL32) is the first bootloader |
| 50 | * to run. So there is no BL2 to load the HW_CONFIG dtb into memory |
| 51 | * before control is passed to SP_MIN. |
| 52 | * Also, BL2 skips loading HW_CONFIG dtb for BL2_AT_EL3 builds. |
| 53 | */ |
| 54 | #if !RESET_TO_SP_MIN && !BL2_AT_EL3 |
| 55 | assert(hw_config_dtb != 0U); |
| 56 | |
| 57 | INFO("SP_MIN FCONF: HW_CONFIG address = %p\n", (void *)hw_config_dtb); |
| 58 | fconf_populate("HW_CONFIG", hw_config_dtb); |
| 59 | #endif |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 60 | } |