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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
Andre Przywaraffbacb02019-07-10 17:27:17 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Jens Wiklander52c798e2015-12-07 14:37:10 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00006
Fu Weic2f78442017-05-27 21:21:42 +08007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
Jens Wiklander52c798e2015-12-07 14:37:10 +010010#include <libfdt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
Jens Wiklander52c798e2015-12-07 14:37:10 +010012#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
14#include <arch_helpers.h>
15#include <common/bl_common.h>
16#include <common/debug.h>
17#include <common/desc_image_load.h>
Andre Przywaraffbacb02019-07-10 17:27:17 +010018#include <common/fdt_fixup.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <lib/optee_utils.h>
20#include <lib/utils.h>
21#include <plat/common/platform.h>
22
Isla Mitchelle3631462017-07-14 10:46:32 +010023#include "qemu_private.h"
Jens Wiklander52c798e2015-12-07 14:37:10 +010024
Jens Wiklander52c798e2015-12-07 14:37:10 +010025
Fu Weic2f78442017-05-27 21:21:42 +080026/* Data structure which holds the extents of the trusted SRAM for BL2 */
27static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
28
Jens Wiklandere22b91e2018-09-04 14:07:19 +020029void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
30 u_register_t arg2, u_register_t arg3)
Jens Wiklander52c798e2015-12-07 14:37:10 +010031{
Jens Wiklandere22b91e2018-09-04 14:07:19 +020032 meminfo_t *mem_layout = (void *)arg1;
33
Jens Wiklander52c798e2015-12-07 14:37:10 +010034 /* Initialize the console to provide early debug support */
Michalis Pappascca6cb72018-03-04 15:43:38 +080035 qemu_console_init();
Jens Wiklander52c798e2015-12-07 14:37:10 +010036
37 /* Setup the BL2 memory layout */
38 bl2_tzram_layout = *mem_layout;
39
40 plat_qemu_io_setup();
41}
42
43static void security_setup(void)
44{
45 /*
46 * This is where a TrustZone address space controller and other
47 * security related peripherals, would be configured.
48 */
49}
50
51static void update_dt(void)
52{
53 int ret;
Andrew Walbran9c4d0692020-01-15 14:11:31 +000054 void *fdt = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
Jens Wiklander52c798e2015-12-07 14:37:10 +010055
56 ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
57 if (ret < 0) {
58 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
59 return;
60 }
61
62 if (dt_add_psci_node(fdt)) {
63 ERROR("Failed to add PSCI Device Tree node\n");
64 return;
65 }
66
67 if (dt_add_psci_cpu_enable_methods(fdt)) {
68 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
69 return;
70 }
71
72 ret = fdt_pack(fdt);
73 if (ret < 0)
74 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
75}
76
77void bl2_platform_setup(void)
78{
79 security_setup();
80 update_dt();
81
82 /* TODO Initialize timer */
83}
84
Julius Werner8e0ef0f2019-07-09 14:02:43 -070085#ifdef __aarch64__
Etienne Carriere911de8c2018-02-02 13:23:22 +010086#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
Julius Werner8e0ef0f2019-07-09 14:02:43 -070087#else
88#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
Etienne Carriere911de8c2018-02-02 13:23:22 +010089#endif
90
Jens Wiklander52c798e2015-12-07 14:37:10 +010091void bl2_plat_arch_setup(void)
92{
Etienne Carriere911de8c2018-02-02 13:23:22 +010093 QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
Jens Wiklander52c798e2015-12-07 14:37:10 +010094 bl2_tzram_layout.total_size,
Michalis Pappasba861122018-02-28 14:36:03 +080095 BL_CODE_BASE, BL_CODE_END,
96 BL_RO_DATA_BASE, BL_RO_DATA_END,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090097 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
Jens Wiklander52c798e2015-12-07 14:37:10 +010098}
99
100/*******************************************************************************
101 * Gets SPSR for BL32 entry
102 ******************************************************************************/
103static uint32_t qemu_get_spsr_for_bl32_entry(void)
104{
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700105#ifdef __aarch64__
Jens Wiklander52c798e2015-12-07 14:37:10 +0100106 /*
107 * The Secure Payload Dispatcher service is responsible for
108 * setting the SPSR prior to entry into the BL3-2 image.
109 */
110 return 0;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100111#else
112 return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
113 DISABLE_ALL_EXCEPTIONS);
114#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100115}
116
117/*******************************************************************************
118 * Gets SPSR for BL33 entry
119 ******************************************************************************/
120static uint32_t qemu_get_spsr_for_bl33_entry(void)
121{
Jens Wiklander52c798e2015-12-07 14:37:10 +0100122 uint32_t spsr;
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700123#ifdef __aarch64__
Etienne Carriere911de8c2018-02-02 13:23:22 +0100124 unsigned int mode;
Jens Wiklander52c798e2015-12-07 14:37:10 +0100125
126 /* Figure out what mode we enter the non-secure world in */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000127 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
Jens Wiklander52c798e2015-12-07 14:37:10 +0100128
129 /*
130 * TODO: Consider the possibility of specifying the SPSR in
131 * the FIP ToC and allowing the platform to have a say as
132 * well.
133 */
134 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
Etienne Carriere911de8c2018-02-02 13:23:22 +0100135#else
136 spsr = SPSR_MODE32(MODE32_svc,
137 plat_get_ns_image_entrypoint() & 0x1,
138 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
139#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100140 return spsr;
141}
142
Fu Weic2f78442017-05-27 21:21:42 +0800143static int qemu_bl2_handle_post_image_load(unsigned int image_id)
144{
145 int err = 0;
146 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Etienne Carriere911de8c2018-02-02 13:23:22 +0100147#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200148 bl_mem_params_node_t *pager_mem_params = NULL;
149 bl_mem_params_node_t *paged_mem_params = NULL;
150#endif
Fu Weic2f78442017-05-27 21:21:42 +0800151
152 assert(bl_mem_params);
153
154 switch (image_id) {
Fu Weic2f78442017-05-27 21:21:42 +0800155 case BL32_IMAGE_ID:
Etienne Carriere911de8c2018-02-02 13:23:22 +0100156#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200157 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
158 assert(pager_mem_params);
159
160 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
161 assert(paged_mem_params);
162
163 err = parse_optee_header(&bl_mem_params->ep_info,
164 &pager_mem_params->image_info,
165 &paged_mem_params->image_info);
166 if (err != 0) {
167 WARN("OPTEE header parse error.\n");
168 }
169
Etienne Carriere911de8c2018-02-02 13:23:22 +0100170#if defined(SPD_opteed)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200171 /*
172 * OP-TEE expect to receive DTB address in x2.
173 * This will be copied into x2 by dispatcher.
174 */
Andrew Walbran9c4d0692020-01-15 14:11:31 +0000175 bl_mem_params->ep_info.args.arg3 = ARM_PRELOADED_DTB_BASE;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100176#else /* case AARCH32_SP_OPTEE */
177 bl_mem_params->ep_info.args.arg0 =
178 bl_mem_params->ep_info.args.arg1;
179 bl_mem_params->ep_info.args.arg1 = 0;
Andrew Walbran9c4d0692020-01-15 14:11:31 +0000180 bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100181 bl_mem_params->ep_info.args.arg3 = 0;
182#endif
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200183#endif
Fu Weic2f78442017-05-27 21:21:42 +0800184 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
185 break;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100186
Fu Weic2f78442017-05-27 21:21:42 +0800187 case BL33_IMAGE_ID:
Etienne Carriere911de8c2018-02-02 13:23:22 +0100188#ifdef AARCH32_SP_OPTEE
189 /* AArch32 only core: OP-TEE expects NSec EP in register LR */
190 pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
191 assert(pager_mem_params);
192 pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
193#endif
194
Andrew Walbran9c4d0692020-01-15 14:11:31 +0000195#if ARM_LINUX_KERNEL_AS_BL33
196 /*
197 * According to the file ``Documentation/arm64/booting.txt`` of
198 * the Linux kernel tree, Linux expects the physical address of
199 * the device tree blob (DTB) in x0, while x1-x3 are reserved
200 * for future use and must be 0.
201 */
202 bl_mem_params->ep_info.args.arg0 =
203 (u_register_t)ARM_PRELOADED_DTB_BASE;
204 bl_mem_params->ep_info.args.arg1 = 0U;
205 bl_mem_params->ep_info.args.arg2 = 0U;
206 bl_mem_params->ep_info.args.arg3 = 0U;
207#else
Fu Weic2f78442017-05-27 21:21:42 +0800208 /* BL33 expects to receive the primary CPU MPID (through r0) */
209 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
Andrew Walbran9c4d0692020-01-15 14:11:31 +0000210#endif
211
Fu Weic2f78442017-05-27 21:21:42 +0800212 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
213 break;
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000214 default:
215 /* Do nothing in default case */
216 break;
Fu Weic2f78442017-05-27 21:21:42 +0800217 }
218
219 return err;
220}
221
222/*******************************************************************************
223 * This function can be used by the platforms to update/use image
224 * information for given `image_id`.
225 ******************************************************************************/
226int bl2_plat_handle_post_image_load(unsigned int image_id)
227{
228 return qemu_bl2_handle_post_image_load(image_id);
229}
Jens Wiklander52c798e2015-12-07 14:37:10 +0100230
Etienne Carriere911de8c2018-02-02 13:23:22 +0100231uintptr_t plat_get_ns_image_entrypoint(void)
Jens Wiklander52c798e2015-12-07 14:37:10 +0100232{
233 return NS_IMAGE_OFFSET;
234}