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git01.mediatek.com / filogic / atf / 9c5ee784bcb7c9f04fce640a911945316ac32e25 / . / plat / mediatek / mt8192 / drivers / apusys / mtk_apusys_apc_def.h
blob: b392d6a5c2d76ddba2e6e0f3a0ed50864e7766a2 [file] [log] [blame]
developer282d3df2021-04-20 18:08:35 +0800[diff] [blame]1/*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __MTK_APUSYS_APC_DEF_H__
8#define __MTK_APUSYS_APC_DEF_H__
9
10#include <lib/mmio.h>
11
12enum APUSYS_APC_ERR_STATUS {
13 APUSYS_APC_OK = 0x0,
14
15 APUSYS_APC_ERR_GENERIC = 0x1000,
16 APUSYS_APC_ERR_INVALID_CMD = 0x1001,
17 APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002,
18 APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003,
19 APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004,
20 APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005,
21 APUSYS_APC_ERR_OUT_OF_BOUNDARY = 0x1006,
22 APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED = 0x1007,
23};
24
25enum APUSYS_APC_PERM_TYPE {
26 NO_PROTECTION = 0U,
27 SEC_RW_ONLY = 1U,
28 SEC_RW_NS_R = 2U,
29 FORBIDDEN = 3U,
30 PERM_NUM = 4U,
31};
32
33enum APUSYS_APC_DOMAIN_ID {
34 DOMAIN_0 = 0U,
35 DOMAIN_1 = 1U,
36 DOMAIN_2 = 2U,
37 DOMAIN_3 = 3U,
38 DOMAIN_4 = 4U,
39 DOMAIN_5 = 5U,
40 DOMAIN_6 = 6U,
41 DOMAIN_7 = 7U,
42 DOMAIN_8 = 8U,
43 DOMAIN_9 = 9U,
44 DOMAIN_10 = 10U,
45 DOMAIN_11 = 11U,
46 DOMAIN_12 = 12U,
47 DOMAIN_13 = 13U,
48 DOMAIN_14 = 14U,
49 DOMAIN_15 = 15U,
50};
51
52struct APC_DOM_16 {
53 unsigned char d0_permission;
54 unsigned char d1_permission;
55 unsigned char d2_permission;
56 unsigned char d3_permission;
57 unsigned char d4_permission;
58 unsigned char d5_permission;
59 unsigned char d6_permission;
60 unsigned char d7_permission;
61 unsigned char d8_permission;
62 unsigned char d9_permission;
63 unsigned char d10_permission;
64 unsigned char d11_permission;
65 unsigned char d12_permission;
66 unsigned char d13_permission;
67 unsigned char d14_permission;
68 unsigned char d15_permission;
69};
70
71#define APUSYS_APC_AO_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
72 PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
73 PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \
74 PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \
75 PERM_ATTR14, PERM_ATTR15) \
76 {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
77 (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
78 (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
79 (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
80 (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
81 (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
82 (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
83 (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
84
85#define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL)
86#define apuapc_readl(REG) mmio_read_32((uintptr_t)REG)
87
88/* APUSYS APC AO Registers */
89#define APUSYS_APC_AO_BASE APUSYS_APC_AO_WRAPPER_BASE
90#define APUSYS_APC_CON (APUSYS_APC_AO_BASE + 0x00F00)
91#define APUSYS_SYS0_APC_LOCK_0 (APUSYS_APC_AO_BASE + 0x00700)
92
93/* APUSYS NOC_DPAC_AO Registers */
94#define APUSYS_NOC_DAPC_CON (APUSYS_NOC_DAPC_AO_BASE + 0x00F00)
95
96#define APUSYS_NOC_DAPC_GAP_BOUNDARY 4U
97#define APUSYS_NOC_DAPC_JUMP_GAP 12U
98
99#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U
100#define APUSYS_APC_SYS0_AO_DOM_NUM 16U
101#define APUSYS_APC_SYS0_AO_SLAVE_NUM 59U
102
103#define APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER 11U
104#define APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5 5U
105
106#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U
107#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U
108#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 27U
109
110#endif /* __MTK_APUSYS_APC_DEF_H__ */