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git01.mediatek.com / filogic / atf / 9c411e39721178510d1488203a6f7d7489ac99ef / . / plat / amd / versal2 / include / def.h
blob: 5018702809e4f9910d462f3b2b2574a435a17221 [file] [log] [blame]
Amit Nagal055796f2024-06-05 12:32:38 +0530[diff] [blame]1/*
2 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef DEF_H
10#define DEF_H
11
12#include <plat/arm/common/smccc_def.h>
13#include <plat/common/common_def.h>
14
15#define MAX_INTR_EL3 2
16
17/* List all consoles */
Maheedhar Bollapalli9c411e32024-07-01 07:07:53 +0000[diff] [blame^]18#define VERSAL2_CONSOLE_ID_pl011 1
19#define VERSAL2_CONSOLE_ID_pl011_0 1
20#define VERSAL2_CONSOLE_ID_pl011_1 2
21#define VERSAL2_CONSOLE_ID_dcc 3
22#define VERSAL2_CONSOLE_ID_dtb 4
Amit Nagal055796f2024-06-05 12:32:38 +0530[diff] [blame]23
Maheedhar Bollapalli9c411e32024-07-01 07:07:53 +0000[diff] [blame^]24#define CONSOLE_IS(con) (VERSAL2_CONSOLE_ID_ ## con == VERSAL2_CONSOLE)
25
26/* Runtime console */
27#define RT_CONSOLE_ID_pl011 1
28#define RT_CONSOLE_ID_pl011_0 1
29#define RT_CONSOLE_ID_pl011_1 2
30#define RT_CONSOLE_ID_dcc 3
31#define RT_CONSOLE_ID_dtb 4
32
33#define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME)
Amit Nagal055796f2024-06-05 12:32:38 +0530[diff] [blame]34
35/* List all platforms */
36#define SILICON U(0)
37#define SPP U(1)
38#define EMU U(2)
39#define QEMU U(3)
40#define SPP_MMD U(5)
41#define EMU_MMD U(6)
42#define QEMU_COSIM U(7)
43
44/* For platform detection */
45#define PMC_TAP U(0xF11A0000)
46#define PMC_TAP_VERSION (PMC_TAP + 0x4U)
47# define PLATFORM_MASK GENMASK(27U, 24U)
48# define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
49
50/* Global timer reset */
51#define PSX_CRF U(0xEC200000)
52#define ACPU0_CLK_CTRL U(0x10C)
53#define ACPU_CLK_CTRL_CLKACT BIT(25)
54
55#define RST_APU0_OFFSET U(0x300)
56#define RST_APU_COLD_RESET BIT(0)
57#define RST_APU_WARN_RESET BIT(4)
58#define RST_APU_CLUSTER_COLD_RESET BIT(8)
59#define RST_APU_CLUSTER_WARM_RESET BIT(9)
60
61#define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C)
62
63#define APU_PCLI (0xECB10000ULL)
64#define APU_PCLI_CPU_STEP (0x30ULL)
65#define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP)
66#define APU_PCLI_CLUSTER_OFFSET U(0x8000)
67#define APU_PCLI_CLUSTER_STEP U(0x1000)
68#define PCLI_PREQ_OFFSET U(0x4)
69#define PREQ_CHANGE_REQUEST BIT(0)
70#define PCLI_PSTATE_OFFSET U(0x8)
71#define PCLI_PSTATE_VAL_SET U(0x48)
72#define PCLI_PSTATE_VAL_CLEAR U(0x38)
73
74/* Firmware Image Package */
75#define PRIMARY_CPU U(0)
76
77#define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL)
78#define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \
79 (APU_PCLI_CPU_STEP * (cpu_id))))
80#define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U)
81#define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL)
82#define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \
83 (APU_PCLI_CPU_STEP * (cpu_id))))
84#define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U)
85#define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL)
86#define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \
87 (APU_PCLI_CPU_STEP * (cpu_id))))
88#define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U)
89#define CORE_0_ISR_POWER_OFFSET (0x00000010ULL)
90#define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \
91 (APU_PCLI_CPU_STEP * (cpu_id))))
92#define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001)
93#define CORE_0_IEN_POWER_OFFSET (0x00000018ULL)
94#define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
95 (APU_PCLI_CPU_STEP * (cpu_id))))
96#define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U)
97#define CORE_0_IDS_POWER_OFFSET (0x0000001CULL)
98#define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
99 (APU_PCLI_CPU_STEP * (cpu_id))))
100#define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U)
101#define CORE_PWRDN_EN_BIT_MASK (0x1U)
102
103/*******************************************************************************
104 * memory map related constants
105 ******************************************************************************/
106/* IPP 1.2/SPP 0.9 mapping */
107#define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */
108#define DEVICE0_SIZE U(0x08000000)
109#define DEVICE1_BASE U(0xE2000000) /* gic */
110#define DEVICE1_SIZE U(0x00800000)
111#define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */
112#define DEVICE2_SIZE U(0x01000000)
113#define CRF_BASE U(0xFD1A0000)
114#define CRF_SIZE U(0x00600000)
115#define IPI_BASE U(0xEB300000)
116#define IPI_SIZE U(0x00100000)
117
118/* CRL */
119#define CRL U(0xEB5E0000)
120#define CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C)
121#define CRL_RST_TIMESTAMP_OFFSET U(0x348)
122
123#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
124
125/* IOU SCNTRS */
126#define IOU_SCNTRS U(0xEC920000)
127#define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
128#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
129
130#define IOU_SCNTRS_CONTROL_EN U(1)
131
132#define APU_CLUSTER0 U(0xECC00000)
133#define APU_RVBAR_L_0 U(0x40)
134#define APU_RVBAR_H_0 U(0x44)
135#define APU_CLUSTER_STEP U(0x100000)
136
137#define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504)
Amit Nagalacb6b922024-07-28 20:32:58 -1200[diff] [blame]138#define PMXC_IOU_SLCR_SRAM_CSR U(0xF106104C)
139#define PMXC_IOU_SLCR_PHY_RESET U(0xF1061050)
140#define PMXC_IOU_SLCR_TX_RX_CONFIG_RDY U(0xF1061054)
141#define PMXC_CRP_RST_UFS U(0xF1260340)
Amit Nagal055796f2024-06-05 12:32:38 +0530[diff] [blame]142
143/*******************************************************************************
144 * IRQ constants
145 ******************************************************************************/
146#define IRQ_SEC_PHY_TIMER U(29)
147
148/*******************************************************************************
149 * UART related constants
150 ******************************************************************************/
151#define UART0_BASE U(0xF1920000)
152#define UART1_BASE U(0xF1930000)
153
154#define UART_BAUDRATE 115200
155
Maheedhar Bollapalli9c411e32024-07-01 07:07:53 +0000[diff] [blame^]156#if CONSOLE_IS(pl011) || CONSOLE_IS(dtb)
157#define UART_BASE UART0_BASE
158# define UART_TYPE CONSOLE_PL011
159#elif CONSOLE_IS(pl011_1)
160#define UART_BASE UART1_BASE
161# define UART_TYPE CONSOLE_PL011
162#elif CONSOLE_IS(dcc)
163# define UART_BASE 0x0
164# define UART_TYPE CONSOLE_DCC
165#else
166# error "invalid VERSAL2_CONSOLE"
167#endif
168
169/* Runtime console */
170#if defined(CONSOLE_RUNTIME)
171#if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb)
172# define RT_UART_BASE UART0_BASE
173# define RT_UART_TYPE CONSOLE_PL011
174#elif RT_CONSOLE_IS(pl011_1)
175# define RT_UART_BASE UART1_BASE
176# define RT_UART_TYPE CONSOLE_PL011
177#elif RT_CONSOLE_IS(dcc)
178# define RT_UART_BASE 0x0
179# define RT_UART_TYPE CONSOLE_DCC
Amit Nagal055796f2024-06-05 12:32:38 +0530[diff] [blame]180#else
Maheedhar Bollapalli9c411e32024-07-01 07:07:53 +0000[diff] [blame^]181# error "invalid CONSOLE_RUNTIME"
182#endif
Amit Nagal055796f2024-06-05 12:32:38 +0530[diff] [blame]183#endif
184
185#endif /* DEF_H */