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git01.mediatek.com / filogic / atf / 9bd4b7f3d34d3bae9fa4d5af9cf7a757640c6bce / . / drivers / staging / renesas / rcar / pfc / M3N / pfc_init_m3n.c
blob: 3e17a04e9a0e5f03c71f88d8552b9acc10df513e [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1/*
Marek Vasut246ef172019-06-17 19:04:36 +0200[diff] [blame]2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdint.h> /* for uint32_t */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
9#include <lib/mmio.h>
10
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]11#include "pfc_init_m3n.h"
12#include "rcar_def.h"
Marek Vasut246ef172019-06-17 19:04:36 +0200[diff] [blame]13#include "../pfc_regs.h"
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]14
Marek Vasut9bd4b7f2019-06-17 19:05:26 +0200[diff] [blame^]15#define GPSR0_D15 ((uint32_t)1U << 15U)
16#define GPSR0_D14 ((uint32_t)1U << 14U)
17#define GPSR0_D13 ((uint32_t)1U << 13U)
18#define GPSR0_D12 ((uint32_t)1U << 12U)
19#define GPSR0_D11 ((uint32_t)1U << 11U)
20#define GPSR0_D10 ((uint32_t)1U << 10U)
21#define GPSR0_D9 ((uint32_t)1U << 9U)
22#define GPSR0_D8 ((uint32_t)1U << 8U)
23#define GPSR0_D7 ((uint32_t)1U << 7U)
24#define GPSR0_D6 ((uint32_t)1U << 6U)
25#define GPSR0_D5 ((uint32_t)1U << 5U)
26#define GPSR0_D4 ((uint32_t)1U << 4U)
27#define GPSR0_D3 ((uint32_t)1U << 3U)
28#define GPSR0_D2 ((uint32_t)1U << 2U)
29#define GPSR0_D1 ((uint32_t)1U << 1U)
30#define GPSR0_D0 ((uint32_t)1U << 0U)
31#define GPSR1_CLKOUT ((uint32_t)1U << 28U)
32#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
33#define GPSR1_WE1 ((uint32_t)1U << 26U)
34#define GPSR1_WE0 ((uint32_t)1U << 25U)
35#define GPSR1_RD_WR ((uint32_t)1U << 24U)
36#define GPSR1_RD ((uint32_t)1U << 23U)
37#define GPSR1_BS ((uint32_t)1U << 22U)
38#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
39#define GPSR1_CS0 ((uint32_t)1U << 20U)
40#define GPSR1_A19 ((uint32_t)1U << 19U)
41#define GPSR1_A18 ((uint32_t)1U << 18U)
42#define GPSR1_A17 ((uint32_t)1U << 17U)
43#define GPSR1_A16 ((uint32_t)1U << 16U)
44#define GPSR1_A15 ((uint32_t)1U << 15U)
45#define GPSR1_A14 ((uint32_t)1U << 14U)
46#define GPSR1_A13 ((uint32_t)1U << 13U)
47#define GPSR1_A12 ((uint32_t)1U << 12U)
48#define GPSR1_A11 ((uint32_t)1U << 11U)
49#define GPSR1_A10 ((uint32_t)1U << 10U)
50#define GPSR1_A9 ((uint32_t)1U << 9U)
51#define GPSR1_A8 ((uint32_t)1U << 8U)
52#define GPSR1_A7 ((uint32_t)1U << 7U)
53#define GPSR1_A6 ((uint32_t)1U << 6U)
54#define GPSR1_A5 ((uint32_t)1U << 5U)
55#define GPSR1_A4 ((uint32_t)1U << 4U)
56#define GPSR1_A3 ((uint32_t)1U << 3U)
57#define GPSR1_A2 ((uint32_t)1U << 2U)
58#define GPSR1_A1 ((uint32_t)1U << 1U)
59#define GPSR1_A0 ((uint32_t)1U << 0U)
60#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
61#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
62#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
63#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
64#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
65#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
66#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
67#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
68#define GPSR2_PWM0 ((uint32_t)1U << 6U)
69#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
70#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
71#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
72#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
73#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
74#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
75#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
76#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
77#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
78#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
79#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
80#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
81#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
82#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
83#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
84#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
85#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
86#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
87#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
88#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
89#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
90#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
91#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
92#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
93#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
94#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
95#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
96#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
97#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
98#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
99#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
100#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
101#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
102#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
103#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
104#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
105#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
106#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
107#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
108#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
109#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
110#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
111#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
112#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
113#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
114#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
115#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
116#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
117#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
118#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
119#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
120#define GPSR5_HTX0 ((uint32_t)1U << 14U)
121#define GPSR5_HRX0 ((uint32_t)1U << 13U)
122#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
123#define GPSR5_RX2_A ((uint32_t)1U << 11U)
124#define GPSR5_TX2_A ((uint32_t)1U << 10U)
125#define GPSR5_SCK2 ((uint32_t)1U << 9U)
126#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
127#define GPSR5_CTS1 ((uint32_t)1U << 7U)
128#define GPSR5_TX1_A ((uint32_t)1U << 6U)
129#define GPSR5_RX1_A ((uint32_t)1U << 5U)
130#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
131#define GPSR5_CTS0 ((uint32_t)1U << 3U)
132#define GPSR5_TX0 ((uint32_t)1U << 2U)
133#define GPSR5_RX0 ((uint32_t)1U << 1U)
134#define GPSR5_SCK0 ((uint32_t)1U << 0U)
135#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
136#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
137#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
138#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
139#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
140#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
141#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
142#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
143#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
144#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
145#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
146#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
147#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
148#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
149#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
150#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
151#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
152#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
153#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
154#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
155#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
156#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
157#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
158#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
159#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
160#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
161#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
162#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
163#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
164#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
165#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
166#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
167#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
168#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
169#define GPSR7_AVS2 ((uint32_t)1U << 1U)
170#define GPSR7_AVS1 ((uint32_t)1U << 0U)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]171
Marek Vasut9bd4b7f2019-06-17 19:05:26 +0200[diff] [blame^]172#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
173#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
174#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
175#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
176#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
177#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
178#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
179#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]180
Marek Vasut9bd4b7f2019-06-17 19:05:26 +0200[diff] [blame^]181#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
182#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
183#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
184#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
185#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
186#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
187#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
188#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
189#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
190#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
191#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
192#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
193#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
194#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
195#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
196#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
197#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
198#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
199#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
200#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
201#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
202#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
203#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
204#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
205#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
206#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
207#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
208#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
209#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
210#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]211
Marek Vasut9bd4b7f2019-06-17 19:05:26 +0200[diff] [blame^]212#define DRVCTRL0_MASK (0xCCCCCCCCU)
213#define DRVCTRL1_MASK (0xCCCCCCC8U)
214#define DRVCTRL2_MASK (0x88888888U)
215#define DRVCTRL3_MASK (0x88888888U)
216#define DRVCTRL4_MASK (0x88888888U)
217#define DRVCTRL5_MASK (0x88888888U)
218#define DRVCTRL6_MASK (0x88888888U)
219#define DRVCTRL7_MASK (0x88888888U)
220#define DRVCTRL8_MASK (0x88888888U)
221#define DRVCTRL9_MASK (0x88888888U)
222#define DRVCTRL10_MASK (0x88888888U)
223#define DRVCTRL11_MASK (0x888888CCU)
224#define DRVCTRL12_MASK (0xCCCFFFCFU)
225#define DRVCTRL13_MASK (0xCC888888U)
226#define DRVCTRL14_MASK (0x88888888U)
227#define DRVCTRL15_MASK (0x88888888U)
228#define DRVCTRL16_MASK (0x88888888U)
229#define DRVCTRL17_MASK (0x88888888U)
230#define DRVCTRL18_MASK (0x88888888U)
231#define DRVCTRL19_MASK (0x88888888U)
232#define DRVCTRL20_MASK (0x88888888U)
233#define DRVCTRL21_MASK (0x88888888U)
234#define DRVCTRL22_MASK (0x88888888U)
235#define DRVCTRL23_MASK (0x88888888U)
236#define DRVCTRL24_MASK (0x8888888FU)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]237
Marek Vasut9bd4b7f2019-06-17 19:05:26 +0200[diff] [blame^]238#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
239#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
240#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
241#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
242#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
243#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
244#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
245#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
246#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
247#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
248#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
249#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
250#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
251#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
252#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
253#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
254#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
255#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
256#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
257#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
258#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
259#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
260#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
261#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
262#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
263#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
264#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
265#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
266#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
267#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
268#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
269#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
270#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
271#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
272#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
273#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
274#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
275#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
276#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
277#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
278#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
279#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
280#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
281#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
282#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
283#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
284#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
285#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
286#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
287#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
288#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
289#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
290#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
291#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
292#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
293#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
294#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
295#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
296#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
297#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
298#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
299#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
300#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
301#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
302#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
303#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
304#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
305#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
306#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
307#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
308#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
309#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
310#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
311#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
312#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
313#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
314#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
315#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
316#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
317#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
318#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
319#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
320#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
321#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
322#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
323#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
324#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
325#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
326#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
327#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
328#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
329#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
330#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
331#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
332#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
333#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
334#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
335#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
336#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
337#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
338#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
339#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
340#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
341#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
342#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
343#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
344#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
345#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
346#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
347#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
348#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
349#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
350#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
351#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
352#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
353#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
354#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
355#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
356#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
357#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
358#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
359#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
360#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
361#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
362#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
363#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
364#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
365#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
366#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
367#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
368#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
369#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
370#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
371#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
372#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
373#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
374#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
375#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
376#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
377#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
378#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
379#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
380#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
381#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
382#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
383#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
384#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
385#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
386#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
387#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
388#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
389#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
390#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
391#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
392#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
393#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
394#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
395#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
396#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
397#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
398#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
399#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
400#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
401#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
402#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
403#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
404#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
405#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
406#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
407#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
408#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
409#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
410#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
411#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
412#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
413#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
414#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
415#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
416#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
417#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
418#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
419#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
420#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
421#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
422#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
423#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
424#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
425#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
426#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
427#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
428#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
429#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
430#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
431#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
432#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]433
Marek Vasut9bd4b7f2019-06-17 19:05:26 +0200[diff] [blame^]434#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
435#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
436#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
437#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
438#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
439#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
440#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
441#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
442#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
443#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
444#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
445#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
446#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
447#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
448#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
449#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
450#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
451#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
452#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
453#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
454#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
455#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
456#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
457#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
458#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
459#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
460#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
461#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
462#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
463#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
464#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
465#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
466#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
467#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
468#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
469#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
470#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
471#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
472#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
473#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
474#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
475#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
476#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
477#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
478#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
479#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
480#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
481#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
482#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
483#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
484#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
485#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
486#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
487#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
488#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
489#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
490#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
491#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
492#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
493#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
494#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
495#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
496#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
497#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
498#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
499#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
500#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
501#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
502#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
503#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
504#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
505#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
506#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
507#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
508#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
509#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
510#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
511#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
512#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
513#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
514#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
515#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
516#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
517#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
518#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
519#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
520#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
521#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
522#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
523#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
524#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
525#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
526#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
527#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
528#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
529#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
530#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
531#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
532#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
533#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
534#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
535#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
536#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
537#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
538#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
539#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
540#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
541#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
542#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
543#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
544#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
545#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
546#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
547#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
548#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
549#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
550#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
551#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
552#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
553#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
554#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
555#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
556#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
557#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
558#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
559#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
560#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
561#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
562#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
563#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
564#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
565#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
566#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
567#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
568#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
569#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
570#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
571#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
572#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
573#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]574
575static void pfc_reg_write(uint32_t addr, uint32_t data);
576
577static void pfc_reg_write(uint32_t addr, uint32_t data)
578{
579 mmio_write_32(PFC_PMMR, ~data);
Marek Vasut9bd4b7f2019-06-17 19:05:26 +0200[diff] [blame^]580 mmio_write_32((uintptr_t)addr, data);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]581}
582
583void pfc_init_m3n(void)
584{
585 uint32_t reg;
586
587 /* initialize module select */
588 pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
589 | MOD_SEL0_MSIOF2_A
590 | MOD_SEL0_MSIOF1_A
591 | MOD_SEL0_LBSC_A
592 | MOD_SEL0_IEBUS_A
593 | MOD_SEL0_I2C2_A
594 | MOD_SEL0_I2C1_A
595 | MOD_SEL0_HSCIF4_A
596 | MOD_SEL0_HSCIF3_A
597 | MOD_SEL0_HSCIF1_A
598 | MOD_SEL0_FSO_A
599 | MOD_SEL0_HSCIF2_A
600 | MOD_SEL0_ETHERAVB_A
601 | MOD_SEL0_DRIF3_A
602 | MOD_SEL0_DRIF2_A
603 | MOD_SEL0_DRIF1_A
604 | MOD_SEL0_DRIF0_A
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]605 | MOD_SEL0_CANFD0_A
606 | MOD_SEL0_ADG_A_A);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]607 pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
608 | MOD_SEL1_TSIF0_A
609 | MOD_SEL1_TIMER_TMU_A
610 | MOD_SEL1_SSP1_1_A
611 | MOD_SEL1_SSP1_0_A
612 | MOD_SEL1_SSI_A
613 | MOD_SEL1_SPEED_PULSE_IF_A
614 | MOD_SEL1_SIMCARD_A
615 | MOD_SEL1_SDHI2_A
616 | MOD_SEL1_SCIF4_A
617 | MOD_SEL1_SCIF3_A
618 | MOD_SEL1_SCIF2_A
619 | MOD_SEL1_SCIF1_A
620 | MOD_SEL1_SCIF_A
621 | MOD_SEL1_REMOCON_A
622 | MOD_SEL1_RCAN0_A
623 | MOD_SEL1_PWM6_A
624 | MOD_SEL1_PWM5_A
625 | MOD_SEL1_PWM4_A
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]626 | MOD_SEL1_PWM3_A
627 | MOD_SEL1_PWM2_A
628 | MOD_SEL1_PWM1_A);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]629 pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
630 | MOD_SEL2_I2C_3_A
631 | MOD_SEL2_I2C_0_A
632 | MOD_SEL2_FM_A
633 | MOD_SEL2_SCIF5_A
634 | MOD_SEL2_I2C6_A
635 | MOD_SEL2_NDF_A
636 | MOD_SEL2_SSI2_A
637 | MOD_SEL2_SSI9_A
638 | MOD_SEL2_TIMER_TMU2_A
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]639 | MOD_SEL2_ADG_B_A
640 | MOD_SEL2_ADG_C_A
641 | MOD_SEL2_VIN4_A);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]642
643 /* initialize peripheral function select */
644 pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
645 | IPSR_24_FUNC(0)
646 | IPSR_20_FUNC(0)
647 | IPSR_16_FUNC(0)
648 | IPSR_12_FUNC(0)
649 | IPSR_8_FUNC(0)
650 | IPSR_4_FUNC(0)
651 | IPSR_0_FUNC(0));
652 pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
653 | IPSR_24_FUNC(0)
654 | IPSR_20_FUNC(0)
655 | IPSR_16_FUNC(0)
656 | IPSR_12_FUNC(3)
657 | IPSR_8_FUNC(3)
658 | IPSR_4_FUNC(3)
659 | IPSR_0_FUNC(3));
660 pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
661 | IPSR_24_FUNC(6)
662 | IPSR_20_FUNC(6)
663 | IPSR_16_FUNC(6)
664 | IPSR_12_FUNC(6)
665 | IPSR_8_FUNC(6)
666 | IPSR_4_FUNC(6)
667 | IPSR_0_FUNC(6));
668 pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
669 | IPSR_24_FUNC(6)
670 | IPSR_20_FUNC(6)
671 | IPSR_16_FUNC(6)
672 | IPSR_12_FUNC(6)
673 | IPSR_8_FUNC(0)
674 | IPSR_4_FUNC(0)
675 | IPSR_0_FUNC(0));
676 pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
677 | IPSR_24_FUNC(0)
678 | IPSR_20_FUNC(0)
679 | IPSR_16_FUNC(0)
680 | IPSR_12_FUNC(0)
681 | IPSR_8_FUNC(6)
682 | IPSR_4_FUNC(6)
683 | IPSR_0_FUNC(6));
684 pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
685 | IPSR_24_FUNC(0)
686 | IPSR_20_FUNC(0)
687 | IPSR_16_FUNC(0)
688 | IPSR_12_FUNC(0)
689 | IPSR_8_FUNC(6)
690 | IPSR_4_FUNC(0)
691 | IPSR_0_FUNC(0));
692 pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
693 | IPSR_24_FUNC(6)
694 | IPSR_20_FUNC(6)
695 | IPSR_16_FUNC(6)
696 | IPSR_12_FUNC(6)
697 | IPSR_8_FUNC(0)
698 | IPSR_4_FUNC(0)
699 | IPSR_0_FUNC(0));
700 pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
701 | IPSR_24_FUNC(0)
702 | IPSR_20_FUNC(0)
703 | IPSR_16_FUNC(0)
704 | IPSR_12_FUNC(0)
705 | IPSR_8_FUNC(6)
706 | IPSR_4_FUNC(6)
707 | IPSR_0_FUNC(6));
708 pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
709 | IPSR_24_FUNC(1)
710 | IPSR_20_FUNC(1)
711 | IPSR_16_FUNC(1)
712 | IPSR_12_FUNC(0)
713 | IPSR_8_FUNC(0)
714 | IPSR_4_FUNC(0)
715 | IPSR_0_FUNC(0));
716 pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
717 | IPSR_24_FUNC(0)
718 | IPSR_20_FUNC(0)
719 | IPSR_16_FUNC(0)
720 | IPSR_12_FUNC(0)
721 | IPSR_8_FUNC(0)
722 | IPSR_4_FUNC(0)
723 | IPSR_0_FUNC(0));
724 pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
725 | IPSR_24_FUNC(0)
726 | IPSR_20_FUNC(0)
727 | IPSR_16_FUNC(0)
728 | IPSR_12_FUNC(0)
729 | IPSR_8_FUNC(0)
730 | IPSR_4_FUNC(0)
731 | IPSR_0_FUNC(0));
732 pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
733 | IPSR_24_FUNC(4)
734 | IPSR_20_FUNC(0)
735 | IPSR_16_FUNC(0)
736 | IPSR_12_FUNC(0)
737 | IPSR_8_FUNC(0)
738 | IPSR_4_FUNC(0)
739 | IPSR_0_FUNC(1));
740 pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
741 | IPSR_24_FUNC(0)
742 | IPSR_20_FUNC(0)
743 | IPSR_16_FUNC(0)
744 | IPSR_12_FUNC(0)
745 | IPSR_8_FUNC(4)
746 | IPSR_4_FUNC(0)
747 | IPSR_0_FUNC(0));
748 pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
749 | IPSR_24_FUNC(0)
750 | IPSR_20_FUNC(0)
751 | IPSR_16_FUNC(0)
752 | IPSR_12_FUNC(0)
753 | IPSR_8_FUNC(3)
754 | IPSR_4_FUNC(0)
755 | IPSR_0_FUNC(0));
756 pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
757 | IPSR_24_FUNC(0)
758 | IPSR_20_FUNC(0)
759 | IPSR_16_FUNC(0)
760 | IPSR_12_FUNC(0)
761 | IPSR_8_FUNC(0)
762 | IPSR_4_FUNC(3)
763 | IPSR_0_FUNC(8));
764 pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
765 | IPSR_24_FUNC(0)
766 | IPSR_20_FUNC(0)
767 | IPSR_16_FUNC(0)
768 | IPSR_12_FUNC(0)
769 | IPSR_8_FUNC(0)
770 | IPSR_4_FUNC(0)
771 | IPSR_0_FUNC(0));
772 pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
773 | IPSR_24_FUNC(0)
774 | IPSR_20_FUNC(0)
775 | IPSR_16_FUNC(0)
776 | IPSR_12_FUNC(0)
777 | IPSR_8_FUNC(0)
778 | IPSR_4_FUNC(0)
779 | IPSR_0_FUNC(0));
780 pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
781 | IPSR_24_FUNC(0)
782 | IPSR_20_FUNC(0)
783 | IPSR_16_FUNC(0)
784 | IPSR_12_FUNC(0)
785 | IPSR_8_FUNC(0)
786 | IPSR_4_FUNC(1)
787 | IPSR_0_FUNC(0));
788 pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
789 | IPSR_0_FUNC(0));
790
791 /* initialize GPIO/perihperal function select */
792 pfc_reg_write(PFC_GPSR0, GPSR0_D15
793 | GPSR0_D14
794 | GPSR0_D13
795 | GPSR0_D12
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]796 | GPSR0_D11
797 | GPSR0_D10
798 | GPSR0_D9
799 | GPSR0_D8);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]800 pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
801 | GPSR1_EX_WAIT0_A
802 | GPSR1_A19
803 | GPSR1_A18
804 | GPSR1_A17
805 | GPSR1_A16
806 | GPSR1_A15
807 | GPSR1_A14
808 | GPSR1_A13
809 | GPSR1_A12
810 | GPSR1_A7
811 | GPSR1_A6
812 | GPSR1_A5
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]813 | GPSR1_A4
814 | GPSR1_A3
815 | GPSR1_A2
816 | GPSR1_A1
817 | GPSR1_A0);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]818 pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
819 | GPSR2_AVB_AVTP_MATCH_A
820 | GPSR2_AVB_LINK
821 | GPSR2_AVB_PHY_INT
822 | GPSR2_AVB_MDC
823 | GPSR2_PWM2_A
824 | GPSR2_PWM1_A
825 | GPSR2_IRQ5
826 | GPSR2_IRQ4
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]827 | GPSR2_IRQ3
828 | GPSR2_IRQ2
829 | GPSR2_IRQ1
830 | GPSR2_IRQ0);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]831 pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
832 | GPSR3_SD0_CD
833 | GPSR3_SD1_DAT3
834 | GPSR3_SD1_DAT2
835 | GPSR3_SD1_DAT1
836 | GPSR3_SD1_DAT0
837 | GPSR3_SD0_DAT3
838 | GPSR3_SD0_DAT2
839 | GPSR3_SD0_DAT1
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]840 | GPSR3_SD0_DAT0
841 | GPSR3_SD0_CMD
842 | GPSR3_SD0_CLK);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]843 pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
844 | GPSR4_SD3_DAT6
845 | GPSR4_SD3_DAT3
846 | GPSR4_SD3_DAT2
847 | GPSR4_SD3_DAT1
848 | GPSR4_SD3_DAT0
849 | GPSR4_SD3_CMD
850 | GPSR4_SD3_CLK
851 | GPSR4_SD2_DS
852 | GPSR4_SD2_DAT3
853 | GPSR4_SD2_DAT2
854 | GPSR4_SD2_DAT1
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]855 | GPSR4_SD2_DAT0
856 | GPSR4_SD2_CMD
857 | GPSR4_SD2_CLK);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]858 pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
859 | GPSR5_MSIOF0_SS1
860 | GPSR5_MSIOF0_SYNC
861 | GPSR5_HRTS0
862 | GPSR5_HCTS0
863 | GPSR5_HTX0
864 | GPSR5_HRX0
865 | GPSR5_HSCK0
866 | GPSR5_RX2_A
867 | GPSR5_TX2_A
868 | GPSR5_SCK2
869 | GPSR5_RTS1_TANS
870 | GPSR5_CTS1
871 | GPSR5_TX1_A
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]872 | GPSR5_RX1_A
873 | GPSR5_RTS0_TANS
874 | GPSR5_SCK0);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]875 pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
876 | GPSR6_USB30_PWEN
877 | GPSR6_USB1_OVC
878 | GPSR6_USB1_PWEN
879 | GPSR6_USB0_OVC
880 | GPSR6_USB0_PWEN
881 | GPSR6_AUDIO_CLKB_B
882 | GPSR6_AUDIO_CLKA_A
883 | GPSR6_SSI_SDATA8
884 | GPSR6_SSI_SDATA7
885 | GPSR6_SSI_WS78
886 | GPSR6_SSI_SCK78
887 | GPSR6_SSI_WS6
888 | GPSR6_SSI_SCK6
889 | GPSR6_SSI_SDATA4
890 | GPSR6_SSI_WS4
891 | GPSR6_SSI_SCK4
892 | GPSR6_SSI_SDATA1_A
893 | GPSR6_SSI_SDATA0
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]894 | GPSR6_SSI_WS0129
895 | GPSR6_SSI_SCK0129);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]896 pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]897 | GPSR7_HDMI0_CEC
898 | GPSR7_AVS2
899 | GPSR7_AVS1);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]900
901 /* initialize POC control register */
902 pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
903 | POC_SD3_DAT7_33V
904 | POC_SD3_DAT6_33V
905 | POC_SD3_DAT5_33V
906 | POC_SD3_DAT4_33V
907 | POC_SD3_DAT3_33V
908 | POC_SD3_DAT2_33V
909 | POC_SD3_DAT1_33V
910 | POC_SD3_DAT0_33V
911 | POC_SD3_CMD_33V
912 | POC_SD3_CLK_33V
913 | POC_SD0_DAT3_33V
914 | POC_SD0_DAT2_33V
915 | POC_SD0_DAT1_33V
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]916 | POC_SD0_DAT0_33V
917 | POC_SD0_CMD_33V
918 | POC_SD0_CLK_33V);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]919
920 /* initialize DRV control register */
921 reg = mmio_read_32(PFC_DRVCTRL0);
922 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
923 | DRVCTRL0_QSPI0_MOSI_IO0(3)
924 | DRVCTRL0_QSPI0_MISO_IO1(3)
925 | DRVCTRL0_QSPI0_IO2(3)
926 | DRVCTRL0_QSPI0_IO3(3)
927 | DRVCTRL0_QSPI0_SSL(3)
928 | DRVCTRL0_QSPI1_SPCLK(3)
929 | DRVCTRL0_QSPI1_MOSI_IO0(3));
930 pfc_reg_write(PFC_DRVCTRL0, reg);
931 reg = mmio_read_32(PFC_DRVCTRL1);
932 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
933 | DRVCTRL1_QSPI1_IO2(3)
934 | DRVCTRL1_QSPI1_IO3(3)
935 | DRVCTRL1_QSPI1_SS(3)
936 | DRVCTRL1_RPC_INT(3)
937 | DRVCTRL1_RPC_WP(3)
938 | DRVCTRL1_RPC_RESET(3)
939 | DRVCTRL1_AVB_RX_CTL(7));
940 pfc_reg_write(PFC_DRVCTRL1, reg);
941 reg = mmio_read_32(PFC_DRVCTRL2);
942 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
943 | DRVCTRL2_AVB_RD0(7)
944 | DRVCTRL2_AVB_RD1(7)
945 | DRVCTRL2_AVB_RD2(7)
946 | DRVCTRL2_AVB_RD3(7)
947 | DRVCTRL2_AVB_TX_CTL(3)
948 | DRVCTRL2_AVB_TXC(3)
949 | DRVCTRL2_AVB_TD0(3));
950 pfc_reg_write(PFC_DRVCTRL2, reg);
951 reg = mmio_read_32(PFC_DRVCTRL3);
952 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
953 | DRVCTRL3_AVB_TD2(3)
954 | DRVCTRL3_AVB_TD3(3)
955 | DRVCTRL3_AVB_TXCREFCLK(7)
956 | DRVCTRL3_AVB_MDIO(7)
957 | DRVCTRL3_AVB_MDC(7)
958 | DRVCTRL3_AVB_MAGIC(7)
959 | DRVCTRL3_AVB_PHY_INT(7));
960 pfc_reg_write(PFC_DRVCTRL3, reg);
961 reg = mmio_read_32(PFC_DRVCTRL4);
962 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
963 | DRVCTRL4_AVB_AVTP_MATCH(7)
964 | DRVCTRL4_AVB_AVTP_CAPTURE(7)
965 | DRVCTRL4_IRQ0(7)
966 | DRVCTRL4_IRQ1(7)
967 | DRVCTRL4_IRQ2(7)
968 | DRVCTRL4_IRQ3(7)
969 | DRVCTRL4_IRQ4(7));
970 pfc_reg_write(PFC_DRVCTRL4, reg);
971 reg = mmio_read_32(PFC_DRVCTRL5);
972 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
973 | DRVCTRL5_PWM0(7)
974 | DRVCTRL5_PWM1(7)
975 | DRVCTRL5_PWM2(7)
976 | DRVCTRL5_A0(3)
977 | DRVCTRL5_A1(3)
978 | DRVCTRL5_A2(3)
979 | DRVCTRL5_A3(3));
980 pfc_reg_write(PFC_DRVCTRL5, reg);
981 reg = mmio_read_32(PFC_DRVCTRL6);
982 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
983 | DRVCTRL6_A5(3)
984 | DRVCTRL6_A6(3)
985 | DRVCTRL6_A7(3)
986 | DRVCTRL6_A8(7)
987 | DRVCTRL6_A9(7)
988 | DRVCTRL6_A10(7)
989 | DRVCTRL6_A11(7));
990 pfc_reg_write(PFC_DRVCTRL6, reg);
991 reg = mmio_read_32(PFC_DRVCTRL7);
992 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
993 | DRVCTRL7_A13(3)
994 | DRVCTRL7_A14(3)
995 | DRVCTRL7_A15(3)
996 | DRVCTRL7_A16(3)
997 | DRVCTRL7_A17(3)
998 | DRVCTRL7_A18(3)
999 | DRVCTRL7_A19(3));
1000 pfc_reg_write(PFC_DRVCTRL7, reg);
1001 reg = mmio_read_32(PFC_DRVCTRL8);
1002 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
1003 | DRVCTRL8_CS0(7)
1004 | DRVCTRL8_CS1_A2(7)
1005 | DRVCTRL8_BS(7)
1006 | DRVCTRL8_RD(7)
1007 | DRVCTRL8_RD_W(7)
1008 | DRVCTRL8_WE0(7)
1009 | DRVCTRL8_WE1(7));
1010 pfc_reg_write(PFC_DRVCTRL8, reg);
1011 reg = mmio_read_32(PFC_DRVCTRL9);
1012 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
1013 | DRVCTRL9_PRESETOU(7)
1014 | DRVCTRL9_D0(7)
1015 | DRVCTRL9_D1(7)
1016 | DRVCTRL9_D2(7)
1017 | DRVCTRL9_D3(7)
1018 | DRVCTRL9_D4(7)
1019 | DRVCTRL9_D5(7));
1020 pfc_reg_write(PFC_DRVCTRL9, reg);
1021 reg = mmio_read_32(PFC_DRVCTRL10);
1022 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
1023 | DRVCTRL10_D7(7)
1024 | DRVCTRL10_D8(3)
1025 | DRVCTRL10_D9(3)
1026 | DRVCTRL10_D10(3)
1027 | DRVCTRL10_D11(3)
1028 | DRVCTRL10_D12(3)
1029 | DRVCTRL10_D13(3));
1030 pfc_reg_write(PFC_DRVCTRL10, reg);
1031 reg = mmio_read_32(PFC_DRVCTRL11);
1032 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
1033 | DRVCTRL11_D15(3)
1034 | DRVCTRL11_AVS1(7)
1035 | DRVCTRL11_AVS2(7)
1036 | DRVCTRL11_HDMI0_CEC(7)
1037 | DRVCTRL11_HDMI1_CEC(7)
1038 | DRVCTRL11_DU_DOTCLKIN0(3)
1039 | DRVCTRL11_DU_DOTCLKIN1(3));
1040 pfc_reg_write(PFC_DRVCTRL11, reg);
1041 reg = mmio_read_32(PFC_DRVCTRL12);
1042 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
1043 | DRVCTRL12_DU_DOTCLKIN3(3)
1044 | DRVCTRL12_DU_FSCLKST(3)
1045 | DRVCTRL12_DU_TMS(3));
1046 pfc_reg_write(PFC_DRVCTRL12, reg);
1047 reg = mmio_read_32(PFC_DRVCTRL13);
1048 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
1049 | DRVCTRL13_ASEBRK(3)
1050 | DRVCTRL13_SD0_CLK(7)
1051 | DRVCTRL13_SD0_CMD(7)
1052 | DRVCTRL13_SD0_DAT0(7)
1053 | DRVCTRL13_SD0_DAT1(7)
1054 | DRVCTRL13_SD0_DAT2(7)
1055 | DRVCTRL13_SD0_DAT3(7));
1056 pfc_reg_write(PFC_DRVCTRL13, reg);
1057 reg = mmio_read_32(PFC_DRVCTRL14);
1058 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
1059 | DRVCTRL14_SD1_CMD(7)
1060 | DRVCTRL14_SD1_DAT0(5)
1061 | DRVCTRL14_SD1_DAT1(5)
1062 | DRVCTRL14_SD1_DAT2(5)
1063 | DRVCTRL14_SD1_DAT3(5)
1064 | DRVCTRL14_SD2_CLK(5)
1065 | DRVCTRL14_SD2_CMD(5));
1066 pfc_reg_write(PFC_DRVCTRL14, reg);
1067 reg = mmio_read_32(PFC_DRVCTRL15);
1068 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
1069 | DRVCTRL15_SD2_DAT1(5)
1070 | DRVCTRL15_SD2_DAT2(5)
1071 | DRVCTRL15_SD2_DAT3(5)
1072 | DRVCTRL15_SD2_DS(5)
1073 | DRVCTRL15_SD3_CLK(7)
1074 | DRVCTRL15_SD3_CMD(7)
1075 | DRVCTRL15_SD3_DAT0(7));
1076 pfc_reg_write(PFC_DRVCTRL15, reg);
1077 reg = mmio_read_32(PFC_DRVCTRL16);
1078 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
1079 | DRVCTRL16_SD3_DAT2(7)
1080 | DRVCTRL16_SD3_DAT3(7)
1081 | DRVCTRL16_SD3_DAT4(7)
1082 | DRVCTRL16_SD3_DAT5(7)
1083 | DRVCTRL16_SD3_DAT6(7)
1084 | DRVCTRL16_SD3_DAT7(7)
1085 | DRVCTRL16_SD3_DS(7));
1086 pfc_reg_write(PFC_DRVCTRL16, reg);
1087 reg = mmio_read_32(PFC_DRVCTRL17);
1088 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
1089 | DRVCTRL17_SD0_WP(7)
1090 | DRVCTRL17_SD1_CD(7)
1091 | DRVCTRL17_SD1_WP(7)
1092 | DRVCTRL17_SCK0(7)
1093 | DRVCTRL17_RX0(7)
1094 | DRVCTRL17_TX0(7)
1095 | DRVCTRL17_CTS0(7));
1096 pfc_reg_write(PFC_DRVCTRL17, reg);
1097 reg = mmio_read_32(PFC_DRVCTRL18);
1098 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
1099 | DRVCTRL18_RX1(7)
1100 | DRVCTRL18_TX1(7)
1101 | DRVCTRL18_CTS1(7)
1102 | DRVCTRL18_RTS1_TANS(7)
1103 | DRVCTRL18_SCK2(7)
1104 | DRVCTRL18_TX2(7)
1105 | DRVCTRL18_RX2(7));
1106 pfc_reg_write(PFC_DRVCTRL18, reg);
1107 reg = mmio_read_32(PFC_DRVCTRL19);
1108 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
1109 | DRVCTRL19_HRX0(7)
1110 | DRVCTRL19_HTX0(7)
1111 | DRVCTRL19_HCTS0(7)
1112 | DRVCTRL19_HRTS0(7)
1113 | DRVCTRL19_MSIOF0_SCK(7)
1114 | DRVCTRL19_MSIOF0_SYNC(7)
1115 | DRVCTRL19_MSIOF0_SS1(7));
1116 pfc_reg_write(PFC_DRVCTRL19, reg);
1117 reg = mmio_read_32(PFC_DRVCTRL20);
1118 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
1119 | DRVCTRL20_MSIOF0_SS2(7)
1120 | DRVCTRL20_MSIOF0_RXD(7)
1121 | DRVCTRL20_MLB_CLK(7)
1122 | DRVCTRL20_MLB_SIG(7)
1123 | DRVCTRL20_MLB_DAT(7)
1124 | DRVCTRL20_MLB_REF(7)
1125 | DRVCTRL20_SSI_SCK0129(7));
1126 pfc_reg_write(PFC_DRVCTRL20, reg);
1127 reg = mmio_read_32(PFC_DRVCTRL21);
1128 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
1129 | DRVCTRL21_SSI_SDATA0(7)
1130 | DRVCTRL21_SSI_SDATA1(7)
1131 | DRVCTRL21_SSI_SDATA2(7)
1132 | DRVCTRL21_SSI_SCK34(7)
1133 | DRVCTRL21_SSI_WS34(7)
1134 | DRVCTRL21_SSI_SDATA3(7)
1135 | DRVCTRL21_SSI_SCK4(7));
1136 pfc_reg_write(PFC_DRVCTRL21, reg);
1137 reg = mmio_read_32(PFC_DRVCTRL22);
1138 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
1139 | DRVCTRL22_SSI_SDATA4(7)
1140 | DRVCTRL22_SSI_SCK5(7)
1141 | DRVCTRL22_SSI_WS5(7)
1142 | DRVCTRL22_SSI_SDATA5(7)
1143 | DRVCTRL22_SSI_SCK6(7)
1144 | DRVCTRL22_SSI_WS6(7)
1145 | DRVCTRL22_SSI_SDATA6(7));
1146 pfc_reg_write(PFC_DRVCTRL22, reg);
1147 reg = mmio_read_32(PFC_DRVCTRL23);
1148 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
1149 | DRVCTRL23_SSI_WS78(7)
1150 | DRVCTRL23_SSI_SDATA7(7)
1151 | DRVCTRL23_SSI_SDATA8(7)
1152 | DRVCTRL23_SSI_SDATA9(7)
1153 | DRVCTRL23_AUDIO_CLKA(7)
1154 | DRVCTRL23_AUDIO_CLKB(7)
1155 | DRVCTRL23_USB0_PWEN(7));
1156 pfc_reg_write(PFC_DRVCTRL23, reg);
1157 reg = mmio_read_32(PFC_DRVCTRL24);
1158 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
1159 | DRVCTRL24_USB1_PWEN(7)
1160 | DRVCTRL24_USB1_OVC(7)
1161 | DRVCTRL24_USB30_PWEN(7)
1162 | DRVCTRL24_USB30_OVC(7)
1163 | DRVCTRL24_USB31_PWEN(7)
1164 | DRVCTRL24_USB31_OVC(7));
1165 pfc_reg_write(PFC_DRVCTRL24, reg);
1166
1167 /* initialize LSI pin pull-up/down control */
1168 pfc_reg_write(PFC_PUD0, 0x00005FBFU);
1169 pfc_reg_write(PFC_PUD1, 0x00300FFEU);
1170 pfc_reg_write(PFC_PUD2, 0x330001E6U);
1171 pfc_reg_write(PFC_PUD3, 0x000002E0U);
1172 pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
1173 pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
1174 pfc_reg_write(PFC_PUD6, 0x00000055U);
1175
1176 /* initialize LSI pin pull-enable register */
1177 pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
1178 pfc_reg_write(PFC_PUEN1, 0x00100234U);
1179 pfc_reg_write(PFC_PUEN2, 0x000004C4U);
1180 pfc_reg_write(PFC_PUEN3, 0x00000200U);
1181 pfc_reg_write(PFC_PUEN4, 0x3E000000U);
1182 pfc_reg_write(PFC_PUEN5, 0x1F000805U);
1183 pfc_reg_write(PFC_PUEN6, 0x00000006U);
1184
1185 /* initialize positive/negative logic select */
1186 mmio_write_32(GPIO_POSNEG0, 0x00000000U);
1187 mmio_write_32(GPIO_POSNEG1, 0x00000000U);
1188 mmio_write_32(GPIO_POSNEG2, 0x00000000U);
1189 mmio_write_32(GPIO_POSNEG3, 0x00000000U);
1190 mmio_write_32(GPIO_POSNEG4, 0x00000000U);
1191 mmio_write_32(GPIO_POSNEG5, 0x00000000U);
1192 mmio_write_32(GPIO_POSNEG6, 0x00000000U);
1193
1194 /* initialize general IO/interrupt switching */
1195 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
1196 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
1197 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
1198 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
1199 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
1200 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
1201 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
1202
1203 /* initialize general output register */
1204 mmio_write_32(GPIO_OUTDT1, 0x00000000U);
1205 mmio_write_32(GPIO_OUTDT2, 0x00000400U);
1206 mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
1207 mmio_write_32(GPIO_OUTDT5, 0x00000006U);
1208 mmio_write_32(GPIO_OUTDT6, 0x00003880U);
1209
1210 /* initialize general input/output switching */
1211 mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
1212 mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
1213 mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
1214 mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
1215 mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
Marek Vasut06302992019-03-02 15:34:36 +0100[diff] [blame]1216#if (RCAR_GEN3_ULCB == 1)
1217 mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
1218#else
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1219 mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
Marek Vasut06302992019-03-02 15:34:36 +0100[diff] [blame]1220#endif
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1221 mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
1222}