blob: 674cb3da30f4563f6a20aa7ecb696b2ea010d6de [file] [log] [blame]
Yann Gautier9cdc11a2022-06-07 14:58:17 +02001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
4 */
5
6/*
7 * STM32MP25 DDR4 board configuration
8 * DDR4 2x8Gbits 2x16bits 1200MHz
9 *
10 * version 1
11 * package 1 Package selection (14x14 and 18x18)
12 * memclk 1200MHz (2x DFI clock) + range check
13 * Speed_Bin Worse from JEDEC
14 * width 32 32: full width / 16: half width
15 * ranks 1 Single or Dual rank
16 * density 8Gbits (per 16bit device)
17 * Addressing RBC row/bank interleaving
18 * RDBI No Read DBI
19 */
20
21#define DDR_MEM_NAME "DDR4 2x8Gbits 2x16bits 1200MHz"
22#define DDR_MEM_SPEED 1200000
23#define DDR_MEM_SIZE 0x80000000
24
25#define DDR_MSTR 0x01040010
26#define DDR_MRCTRL0 0x00000030
27#define DDR_MRCTRL1 0x00000000
28#define DDR_MRCTRL2 0x00000000
29#define DDR_DERATEEN 0x00000000
30#define DDR_DERATEINT 0x00000000
31#define DDR_DERATECTL 0x00000000
32#define DDR_PWRCTL 0x00000000
33#define DDR_PWRTMG 0x00130001
34#define DDR_HWLPCTL 0x00000002
35#define DDR_RFSHCTL0 0x00210010
36#define DDR_RFSHCTL1 0x00000000
37#define DDR_RFSHCTL3 0x00000000
38#define DDR_RFSHTMG 0x009200D2
39#define DDR_RFSHTMG1 0x008C0000
40#define DDR_CRCPARCTL0 0x00000000
41#define DDR_CRCPARCTL1 0x00001000
42#define DDR_INIT0 0xC0020002
43#define DDR_INIT1 0x00010002
44#define DDR_INIT2 0x00000D00
45#define DDR_INIT3 0x09400103
46#define DDR_INIT4 0x00180000
47#define DDR_INIT5 0x00100004
48#define DDR_INIT6 0x00080460
49#define DDR_INIT7 0x00000C16
50#define DDR_DIMMCTL 0x00000000
51#define DDR_RANKCTL 0x0000066F
52#define DDR_DRAMTMG0 0x11152815
53#define DDR_DRAMTMG1 0x0004051E
54#define DDR_DRAMTMG2 0x0609060D
55#define DDR_DRAMTMG3 0x0050400C
56#define DDR_DRAMTMG4 0x0904050A
57#define DDR_DRAMTMG5 0x06060403
58#define DDR_DRAMTMG6 0x02020005
59#define DDR_DRAMTMG7 0x00000202
60#define DDR_DRAMTMG8 0x04041007
61#define DDR_DRAMTMG9 0x0002040A
62#define DDR_DRAMTMG10 0x001C180A
63#define DDR_DRAMTMG11 0x4408021C
64#define DDR_DRAMTMG12 0x0C020010
65#define DDR_DRAMTMG13 0x1C200004
66#define DDR_DRAMTMG14 0x000000A0
67#define DDR_DRAMTMG15 0x00000000
68#define DDR_ZQCTL0 0x01000040
69#define DDR_ZQCTL1 0x2000493E
70#define DDR_ZQCTL2 0x00000000
71#define DDR_DFITMG0 0x038F8209
72#define DDR_DFITMG1 0x00080303
73#define DDR_DFILPCFG0 0x07004111
74#define DDR_DFILPCFG1 0x00000000
75#define DDR_DFIUPD0 0xC0300018
76#define DDR_DFIUPD1 0x005700B4
77#define DDR_DFIUPD2 0x80000000
78#define DDR_DFIMISC 0x00000041
79#define DDR_DFITMG2 0x00000F09
80#define DDR_DFITMG3 0x00000000
81#define DDR_DBICTL 0x00000001
82#define DDR_DFIPHYMSTR 0x80000000
83#define DDR_ADDRMAP0 0x0000001F
84#define DDR_ADDRMAP1 0x003F0909
85#define DDR_ADDRMAP2 0x00000700
86#define DDR_ADDRMAP3 0x00000000
87#define DDR_ADDRMAP4 0x00001F1F
88#define DDR_ADDRMAP5 0x070F0707
89#define DDR_ADDRMAP6 0x07070707
90#define DDR_ADDRMAP7 0x00000F0F
91#define DDR_ADDRMAP8 0x00003F01
92#define DDR_ADDRMAP9 0x07070707
93#define DDR_ADDRMAP10 0x07070707
94#define DDR_ADDRMAP11 0x00000007
95#define DDR_ODTCFG 0x06000618
96#define DDR_ODTMAP 0x00000001
97#define DDR_SCHED 0x00000F00
98#define DDR_SCHED1 0x00000000
99#define DDR_PERFHPR1 0x0F000001
100#define DDR_PERFLPR1 0x0F000080
101#define DDR_PERFWR1 0x01000200
102#define DDR_DBG0 0x00000000
103#define DDR_DBG1 0x00000000
104#define DDR_DBGCMD 0x00000000
105#define DDR_SWCTL 0x00000000
106#define DDR_POISONCFG 0x00000000
107#define DDR_PCCFG 0x00000000
108#define DDR_PCFGR_0 0x00004100
109#define DDR_PCFGW_0 0x00004100
110#define DDR_PCTRL_0 0x00000000
111#define DDR_PCFGQOS0_0 0x00200007
112#define DDR_PCFGQOS1_0 0x01000100
113#define DDR_PCFGWQOS0_0 0x00000C07
114#define DDR_PCFGWQOS1_0 0x02000200
115#define DDR_PCFGR_1 0x00004100
116#define DDR_PCFGW_1 0x00004100
117#define DDR_PCTRL_1 0x00000000
118#define DDR_PCFGQOS0_1 0x00200007
119#define DDR_PCFGQOS1_1 0x01000180
120#define DDR_PCFGWQOS0_1 0x00000C07
121#define DDR_PCFGWQOS1_1 0x04000400
122
123#define DDR_UIB_DRAMTYPE 0x00000000
124#define DDR_UIB_DIMMTYPE 0x00000004
125#define DDR_UIB_LP4XMODE 0x00000000
126#define DDR_UIB_NUMDBYTE 0x00000004
127#define DDR_UIB_NUMACTIVEDBYTEDFI0 0x00000004
128#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000000
129#define DDR_UIB_NUMANIB 0x00000008
130#define DDR_UIB_NUMRANK_DFI0 0x00000001
131#define DDR_UIB_NUMRANK_DFI1 0x00000001
132#define DDR_UIB_DRAMDATAWIDTH 0x00000010
133#define DDR_UIB_NUMPSTATES 0x00000001
134#define DDR_UIB_FREQUENCY_0 0x000004B0
135#define DDR_UIB_PLLBYPASS_0 0x00000000
136#define DDR_UIB_DFIFREQRATIO_0 0x00000001
137#define DDR_UIB_DFI1EXISTS 0x00000001
138#define DDR_UIB_TRAIN2D 0x00000000
139#define DDR_UIB_HARDMACROVER 0x00000003
140#define DDR_UIB_READDBIENABLE_0 0x00000000
141#define DDR_UIB_DFIMODE 0x00000000
142
143#define DDR_UIA_LP4RXPREAMBLEMODE_0 0x00000000
144#define DDR_UIA_LP4POSTAMBLEEXT_0 0x00000000
145#define DDR_UIA_D4RXPREAMBLELENGTH_0 0x00000000
146#define DDR_UIA_D4TXPREAMBLELENGTH_0 0x00000000
147#define DDR_UIA_EXTCALRESVAL 0x00000000
148#define DDR_UIA_IS2TTIMING_0 0x00000000
149#define DDR_UIA_ODTIMPEDANCE_0 0x00000035
150#define DDR_UIA_TXIMPEDANCE_0 0x00000028
151#define DDR_UIA_ATXIMPEDANCE 0x00000028
152#define DDR_UIA_MEMALERTEN 0x00000000
153#define DDR_UIA_MEMALERTPUIMP 0x00000000
154#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
155#define DDR_UIA_MEMALERTSYNCBYPASS 0x00000000
156#define DDR_UIA_DISDYNADRTRI_0 0x00000001
157#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x00000000
158#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000000
159#define DDR_UIA_WDQSEXT 0x00000000
160#define DDR_UIA_CALINTERVAL 0x00000009
161#define DDR_UIA_CALONCE 0x00000000
162#define DDR_UIA_LP4RL_0 0x00000000
163#define DDR_UIA_LP4WL_0 0x00000000
164#define DDR_UIA_LP4WLS_0 0x00000000
165#define DDR_UIA_LP4DBIRD_0 0x00000000
166#define DDR_UIA_LP4DBIWR_0 0x00000000
167#define DDR_UIA_LP4NWR_0 0x00000000
168#define DDR_UIA_LP4LOWPOWERDRV 0x00000000
169#define DDR_UIA_DRAMBYTESWAP 0x00000000
170#define DDR_UIA_RXENBACKOFF 0x00000000
171#define DDR_UIA_TRAINSEQUENCECTRL 0x00000000
172#define DDR_UIA_SNPSUMCTLOPT 0x00000000
173#define DDR_UIA_SNPSUMCTLF0RC5X_0 0x00000000
174#define DDR_UIA_TXSLEWRISEDQ_0 0x0000000F
175#define DDR_UIA_TXSLEWFALLDQ_0 0x0000000F
176#define DDR_UIA_TXSLEWRISEAC 0x0000000F
177#define DDR_UIA_TXSLEWFALLAC 0x0000000F
178#define DDR_UIA_DISABLERETRAINING 0x00000001
179#define DDR_UIA_DISABLEPHYUPDATE 0x00000000
180#define DDR_UIA_ENABLEHIGHCLKSKEWFIX 0x00000000
181#define DDR_UIA_DISABLEUNUSEDADDRLNS 0x00000001
182#define DDR_UIA_PHYINITSEQUENCENUM 0x00000000
183#define DDR_UIA_ENABLEDFICSPOLARITYFIX 0x00000000
184#define DDR_UIA_PHYVREF 0x0000005E
185#define DDR_UIA_SEQUENCECTRL_0 0x0000031F
186
187#define DDR_UIM_MR0_0 0x00000940
188#define DDR_UIM_MR1_0 0x00000103
189#define DDR_UIM_MR2_0 0x00000018
190#define DDR_UIM_MR3_0 0x00000000
191#define DDR_UIM_MR4_0 0x00000008
192#define DDR_UIM_MR5_0 0x00000460
193#define DDR_UIM_MR6_0 0x00000C16
194#define DDR_UIM_MR11_0 0x00000000
195#define DDR_UIM_MR12_0 0x00000000
196#define DDR_UIM_MR13_0 0x00000000
197#define DDR_UIM_MR14_0 0x00000000
198#define DDR_UIM_MR22_0 0x00000000
199
200#define DDR_UIS_SWIZZLE_0 0x0000000C
201#define DDR_UIS_SWIZZLE_1 0x00000005
202#define DDR_UIS_SWIZZLE_2 0x00000013
203#define DDR_UIS_SWIZZLE_3 0x0000001A
204#define DDR_UIS_SWIZZLE_4 0x00000009
205#define DDR_UIS_SWIZZLE_5 0x00000003
206#define DDR_UIS_SWIZZLE_6 0x00000001
207#define DDR_UIS_SWIZZLE_7 0x00000019
208#define DDR_UIS_SWIZZLE_8 0x00000007
209#define DDR_UIS_SWIZZLE_9 0x00000004
210#define DDR_UIS_SWIZZLE_10 0x0000000A
211#define DDR_UIS_SWIZZLE_11 0x0000000D
212#define DDR_UIS_SWIZZLE_12 0x00000014
213#define DDR_UIS_SWIZZLE_13 0x00000000
214#define DDR_UIS_SWIZZLE_14 0x00000000
215#define DDR_UIS_SWIZZLE_15 0x00000000
216#define DDR_UIS_SWIZZLE_16 0x00000000
217#define DDR_UIS_SWIZZLE_17 0x00000000
218#define DDR_UIS_SWIZZLE_18 0x00000006
219#define DDR_UIS_SWIZZLE_19 0x0000000B
220#define DDR_UIS_SWIZZLE_20 0x00000000
221#define DDR_UIS_SWIZZLE_21 0x00000000
222#define DDR_UIS_SWIZZLE_22 0x00000000
223#define DDR_UIS_SWIZZLE_23 0x00000008
224#define DDR_UIS_SWIZZLE_24 0x00000002
225#define DDR_UIS_SWIZZLE_25 0x00000018
226#define DDR_UIS_SWIZZLE_26 0x1A13050C
227#define DDR_UIS_SWIZZLE_27 0x19010309
228#define DDR_UIS_SWIZZLE_28 0x0D0A0407
229#define DDR_UIS_SWIZZLE_29 0x00000014
230#define DDR_UIS_SWIZZLE_30 0x000B0600
231#define DDR_UIS_SWIZZLE_31 0x02080000
232#define DDR_UIS_SWIZZLE_32 0x00000018
233#define DDR_UIS_SWIZZLE_33 0x00000000
234#define DDR_UIS_SWIZZLE_34 0x00000000
235#define DDR_UIS_SWIZZLE_35 0x00000000
236#define DDR_UIS_SWIZZLE_36 0x00000000
237#define DDR_UIS_SWIZZLE_37 0x00000000
238#define DDR_UIS_SWIZZLE_38 0x00000000
239#define DDR_UIS_SWIZZLE_39 0x00000000
240#define DDR_UIS_SWIZZLE_40 0x00000000
241#define DDR_UIS_SWIZZLE_41 0x00000000
242#define DDR_UIS_SWIZZLE_42 0x00000000
243#define DDR_UIS_SWIZZLE_43 0x00000000
244
245#include "stm32mp25-ddr.dtsi"