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Yann Gautier5380b0d2018-10-15 09:36:04 +02001/*
Yann Gautierdbb9f572020-06-12 12:17:17 +02002 * Copyright (c) 2018-2020, STMicroelectronics - All Rights Reserved
Yann Gautier5380b0d2018-10-15 09:36:04 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <errno.h>
9#include <string.h>
10
Yann Gautier57e282b2019-01-07 11:17:24 +010011#include <libfdt.h>
12
13#include <platform_def.h>
14
Yann Gautier5380b0d2018-10-15 09:36:04 +020015#include <arch.h>
16#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <common/debug.h>
18#include <drivers/delay_timer.h>
19#include <drivers/mmc.h>
Yann Gautier038bff22019-01-17 19:17:47 +010020#include <drivers/st/stm32_gpio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <drivers/st/stm32_sdmmc2.h>
Yann Gautiera2e2a302019-02-14 11:13:39 +010022#include <drivers/st/stm32mp_reset.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <lib/mmio.h>
24#include <lib/utils.h>
25#include <plat/common/platform.h>
26
Yann Gautier5380b0d2018-10-15 09:36:04 +020027/* Registers offsets */
28#define SDMMC_POWER 0x00U
29#define SDMMC_CLKCR 0x04U
30#define SDMMC_ARGR 0x08U
31#define SDMMC_CMDR 0x0CU
32#define SDMMC_RESPCMDR 0x10U
33#define SDMMC_RESP1R 0x14U
34#define SDMMC_RESP2R 0x18U
35#define SDMMC_RESP3R 0x1CU
36#define SDMMC_RESP4R 0x20U
37#define SDMMC_DTIMER 0x24U
38#define SDMMC_DLENR 0x28U
39#define SDMMC_DCTRLR 0x2CU
40#define SDMMC_DCNTR 0x30U
41#define SDMMC_STAR 0x34U
42#define SDMMC_ICR 0x38U
43#define SDMMC_MASKR 0x3CU
44#define SDMMC_ACKTIMER 0x40U
45#define SDMMC_IDMACTRLR 0x50U
46#define SDMMC_IDMABSIZER 0x54U
47#define SDMMC_IDMABASE0R 0x58U
48#define SDMMC_IDMABASE1R 0x5CU
49#define SDMMC_FIFOR 0x80U
50
51/* SDMMC power control register */
52#define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
53#define SDMMC_POWER_DIRPOL BIT(4)
54
55/* SDMMC clock control register */
56#define SDMMC_CLKCR_WIDBUS_4 BIT(14)
57#define SDMMC_CLKCR_WIDBUS_8 BIT(15)
58#define SDMMC_CLKCR_NEGEDGE BIT(16)
59#define SDMMC_CLKCR_HWFC_EN BIT(17)
60#define SDMMC_CLKCR_SELCLKRX_0 BIT(20)
61
62/* SDMMC command register */
63#define SDMMC_CMDR_CMDTRANS BIT(6)
64#define SDMMC_CMDR_CMDSTOP BIT(7)
65#define SDMMC_CMDR_WAITRESP GENMASK(9, 8)
66#define SDMMC_CMDR_WAITRESP_SHORT BIT(8)
67#define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9)
68#define SDMMC_CMDR_CPSMEN BIT(12)
69
70/* SDMMC data control register */
71#define SDMMC_DCTRLR_DTEN BIT(0)
72#define SDMMC_DCTRLR_DTDIR BIT(1)
73#define SDMMC_DCTRLR_DTMODE GENMASK(3, 2)
Yann Gautier5380b0d2018-10-15 09:36:04 +020074#define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4)
Yann Gautier6d9e6a02019-06-11 20:03:07 +020075#define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4
Yann Gautier5380b0d2018-10-15 09:36:04 +020076#define SDMMC_DCTRLR_FIFORST BIT(13)
77
78#define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \
79 SDMMC_DCTRLR_DTDIR | \
80 SDMMC_DCTRLR_DTMODE | \
81 SDMMC_DCTRLR_DBLOCKSIZE)
Yann Gautier5380b0d2018-10-15 09:36:04 +020082
83/* SDMMC status register */
84#define SDMMC_STAR_CCRCFAIL BIT(0)
85#define SDMMC_STAR_DCRCFAIL BIT(1)
86#define SDMMC_STAR_CTIMEOUT BIT(2)
87#define SDMMC_STAR_DTIMEOUT BIT(3)
88#define SDMMC_STAR_TXUNDERR BIT(4)
89#define SDMMC_STAR_RXOVERR BIT(5)
90#define SDMMC_STAR_CMDREND BIT(6)
91#define SDMMC_STAR_CMDSENT BIT(7)
92#define SDMMC_STAR_DATAEND BIT(8)
93#define SDMMC_STAR_DBCKEND BIT(10)
Yann Gautiere88fdd72018-11-30 15:22:11 +010094#define SDMMC_STAR_DPSMACT BIT(12)
Yann Gautier5380b0d2018-10-15 09:36:04 +020095#define SDMMC_STAR_RXFIFOHF BIT(15)
96#define SDMMC_STAR_RXFIFOE BIT(19)
97#define SDMMC_STAR_IDMATE BIT(27)
98#define SDMMC_STAR_IDMABTC BIT(28)
99
100/* SDMMC DMA control register */
101#define SDMMC_IDMACTRLR_IDMAEN BIT(0)
102
103#define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \
104 SDMMC_STAR_DCRCFAIL | \
105 SDMMC_STAR_CTIMEOUT | \
106 SDMMC_STAR_DTIMEOUT | \
107 SDMMC_STAR_TXUNDERR | \
108 SDMMC_STAR_RXOVERR | \
109 SDMMC_STAR_CMDREND | \
110 SDMMC_STAR_CMDSENT | \
111 SDMMC_STAR_DATAEND | \
112 SDMMC_STAR_DBCKEND | \
113 SDMMC_STAR_IDMATE | \
114 SDMMC_STAR_IDMABTC)
115
Etienne Carrieref02647a2019-12-08 08:14:40 +0100116#define TIMEOUT_US_1_MS 1000U
Yann Gautier2299d572019-02-14 11:14:39 +0100117#define TIMEOUT_US_10_MS 10000U
118#define TIMEOUT_US_1_S 1000000U
Yann Gautier5380b0d2018-10-15 09:36:04 +0200119
120#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
121
122static void stm32_sdmmc2_init(void);
123static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd);
124static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd);
125static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width);
126static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size);
127static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size);
128static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size);
129
130static const struct mmc_ops stm32_sdmmc2_ops = {
131 .init = stm32_sdmmc2_init,
132 .send_cmd = stm32_sdmmc2_send_cmd,
133 .set_ios = stm32_sdmmc2_set_ios,
134 .prepare = stm32_sdmmc2_prepare,
135 .read = stm32_sdmmc2_read,
136 .write = stm32_sdmmc2_write,
137};
138
139static struct stm32_sdmmc2_params sdmmc2_params;
140
141#pragma weak plat_sdmmc2_use_dma
142bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory)
143{
144 return false;
145}
146
147static void stm32_sdmmc2_init(void)
148{
149 uint32_t clock_div;
Yann Gautier3194afe2019-05-28 11:54:50 +0200150 uint32_t freq = STM32MP_MMC_INIT_FREQ;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200151 uintptr_t base = sdmmc2_params.reg_base;
152
Yann Gautier3194afe2019-05-28 11:54:50 +0200153 if (sdmmc2_params.max_freq != 0U) {
154 freq = MIN(sdmmc2_params.max_freq, freq);
155 }
156
157 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200158
159 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
160 sdmmc2_params.negedge |
161 sdmmc2_params.pin_ckin);
162
163 mmio_write_32(base + SDMMC_POWER,
164 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol);
165
166 mdelay(1);
167}
168
169static int stm32_sdmmc2_stop_transfer(void)
170{
171 struct mmc_cmd cmd_stop;
172
173 zeromem(&cmd_stop, sizeof(struct mmc_cmd));
174
175 cmd_stop.cmd_idx = MMC_CMD(12);
176 cmd_stop.resp_type = MMC_RESPONSE_R1B;
177
178 return stm32_sdmmc2_send_cmd(&cmd_stop);
179}
180
181static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
182{
Yann Gautier2299d572019-02-14 11:14:39 +0100183 uint64_t timeout;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200184 uint32_t flags_cmd, status;
185 uint32_t flags_data = 0;
186 int err = 0;
187 uintptr_t base = sdmmc2_params.reg_base;
Yann Gautier2299d572019-02-14 11:14:39 +0100188 unsigned int cmd_reg, arg_reg;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200189
190 if (cmd == NULL) {
191 return -EINVAL;
192 }
193
194 flags_cmd = SDMMC_STAR_CTIMEOUT;
195 arg_reg = cmd->cmd_arg;
196
197 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) {
198 mmio_write_32(base + SDMMC_CMDR, 0);
199 }
200
201 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN;
202
203 if (cmd->resp_type == 0U) {
204 flags_cmd |= SDMMC_STAR_CMDSENT;
205 }
206
207 if ((cmd->resp_type & MMC_RSP_48) != 0U) {
208 if ((cmd->resp_type & MMC_RSP_136) != 0U) {
209 flags_cmd |= SDMMC_STAR_CMDREND;
210 cmd_reg |= SDMMC_CMDR_WAITRESP;
211 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) {
212 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL;
213 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT;
214 } else {
215 flags_cmd |= SDMMC_STAR_CMDREND;
216 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC;
217 }
218 }
219
220 switch (cmd->cmd_idx) {
221 case MMC_CMD(1):
222 arg_reg |= OCR_POWERUP;
223 break;
224 case MMC_CMD(8):
225 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
226 cmd_reg |= SDMMC_CMDR_CMDTRANS;
227 }
228 break;
229 case MMC_CMD(12):
230 cmd_reg |= SDMMC_CMDR_CMDSTOP;
231 break;
232 case MMC_CMD(17):
233 case MMC_CMD(18):
234 cmd_reg |= SDMMC_CMDR_CMDTRANS;
235 if (sdmmc2_params.use_dma) {
236 flags_data |= SDMMC_STAR_DCRCFAIL |
237 SDMMC_STAR_DTIMEOUT |
238 SDMMC_STAR_DATAEND |
239 SDMMC_STAR_RXOVERR |
240 SDMMC_STAR_IDMATE;
241 }
242 break;
243 case MMC_ACMD(41):
244 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4;
245 break;
246 case MMC_ACMD(51):
247 cmd_reg |= SDMMC_CMDR_CMDTRANS;
248 if (sdmmc2_params.use_dma) {
249 flags_data |= SDMMC_STAR_DCRCFAIL |
250 SDMMC_STAR_DTIMEOUT |
251 SDMMC_STAR_DATAEND |
252 SDMMC_STAR_RXOVERR |
253 SDMMC_STAR_IDMATE |
254 SDMMC_STAR_DBCKEND;
255 }
256 break;
257 default:
258 break;
259 }
260
Yann Gautier10454222020-06-12 14:14:26 +0200261 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
262
263 /*
264 * Clear the SDMMC_DCTRLR if the command does not await data.
265 * Skip CMD55 as the next command could be data related, and
266 * the register could have been set in prepare function.
267 */
268 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) &&
269 (cmd->cmd_idx != MMC_CMD(55))) {
270 mmio_write_32(base + SDMMC_DCTRLR, 0U);
271 }
272
Yann Gautier5380b0d2018-10-15 09:36:04 +0200273 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) {
274 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
275 }
276
277 mmio_write_32(base + SDMMC_ARGR, arg_reg);
278
279 mmio_write_32(base + SDMMC_CMDR, cmd_reg);
280
Yann Gautiere88fdd72018-11-30 15:22:11 +0100281 status = mmio_read_32(base + SDMMC_STAR);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200282
Yann Gautier2299d572019-02-14 11:14:39 +0100283 timeout = timeout_init_us(TIMEOUT_US_10_MS);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200284
Yann Gautiere88fdd72018-11-30 15:22:11 +0100285 while ((status & flags_cmd) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +0100286 if (timeout_elapsed(timeout)) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200287 err = -ETIMEDOUT;
288 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
289 __func__, cmd->cmd_idx, status);
Yann Gautiere88fdd72018-11-30 15:22:11 +0100290 goto err_exit;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200291 }
Yann Gautier5380b0d2018-10-15 09:36:04 +0200292
Yann Gautiere88fdd72018-11-30 15:22:11 +0100293 status = mmio_read_32(base + SDMMC_STAR);
294 }
295
296 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200297 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) {
298 err = -ETIMEDOUT;
299 /*
300 * Those timeouts can occur, and framework will handle
301 * the retries. CMD8 is expected to return this timeout
302 * for eMMC
303 */
304 if (!((cmd->cmd_idx == MMC_CMD(1)) ||
305 (cmd->cmd_idx == MMC_CMD(13)) ||
306 ((cmd->cmd_idx == MMC_CMD(8)) &&
307 (cmd->resp_type == MMC_RESPONSE_R7)))) {
308 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n",
309 __func__, cmd->cmd_idx, status);
310 }
311 } else {
312 err = -EIO;
313 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n",
314 __func__, cmd->cmd_idx, status);
315 }
Yann Gautiere88fdd72018-11-30 15:22:11 +0100316
317 goto err_exit;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200318 }
319
Yann Gautiere88fdd72018-11-30 15:22:11 +0100320 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200321 if ((cmd->cmd_idx == MMC_CMD(9)) &&
322 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) {
323 /* Need to invert response to match CSD structure */
324 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R);
325 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R);
326 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R);
327 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R);
328 } else {
329 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R);
330 if ((cmd_reg & SDMMC_CMDR_WAITRESP) ==
331 SDMMC_CMDR_WAITRESP) {
332 cmd->resp_data[1] = mmio_read_32(base +
333 SDMMC_RESP2R);
334 cmd->resp_data[2] = mmio_read_32(base +
335 SDMMC_RESP3R);
336 cmd->resp_data[3] = mmio_read_32(base +
337 SDMMC_RESP4R);
338 }
339 }
340 }
341
Yann Gautiere88fdd72018-11-30 15:22:11 +0100342 if (flags_data == 0U) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200343 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
344
Yann Gautiere88fdd72018-11-30 15:22:11 +0100345 return 0;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200346 }
347
Yann Gautiere88fdd72018-11-30 15:22:11 +0100348 status = mmio_read_32(base + SDMMC_STAR);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200349
Yann Gautier2299d572019-02-14 11:14:39 +0100350 timeout = timeout_init_us(TIMEOUT_US_10_MS);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200351
Yann Gautiere88fdd72018-11-30 15:22:11 +0100352 while ((status & flags_data) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +0100353 if (timeout_elapsed(timeout)) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200354 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
355 __func__, cmd->cmd_idx, status);
356 err = -ETIMEDOUT;
Yann Gautiere88fdd72018-11-30 15:22:11 +0100357 goto err_exit;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200358 }
Yann Gautiere88fdd72018-11-30 15:22:11 +0100359
360 status = mmio_read_32(base + SDMMC_STAR);
361 };
Yann Gautier5380b0d2018-10-15 09:36:04 +0200362
363 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL |
364 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR |
365 SDMMC_STAR_IDMATE)) != 0U) {
366 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__,
367 cmd->cmd_idx, status);
368 err = -EIO;
369 }
370
Yann Gautiere88fdd72018-11-30 15:22:11 +0100371err_exit:
Yann Gautier5380b0d2018-10-15 09:36:04 +0200372 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
373 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
374
Yann Gautier2299d572019-02-14 11:14:39 +0100375 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) {
Yann Gautiere88fdd72018-11-30 15:22:11 +0100376 int ret_stop = stm32_sdmmc2_stop_transfer();
377
378 if (ret_stop != 0) {
379 return ret_stop;
380 }
Yann Gautier5380b0d2018-10-15 09:36:04 +0200381 }
382
383 return err;
384}
385
386static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd)
387{
Yann Gautierdbb9f572020-06-12 12:17:17 +0200388 uint8_t retry;
389 int err;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200390
391 assert(cmd != NULL);
392
Yann Gautierdbb9f572020-06-12 12:17:17 +0200393 for (retry = 0U; retry < 3U; retry++) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200394 err = stm32_sdmmc2_send_cmd_req(cmd);
395 if (err == 0) {
Yann Gautierdbb9f572020-06-12 12:17:17 +0200396 return 0;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200397 }
398
399 if ((cmd->cmd_idx == MMC_CMD(1)) ||
400 (cmd->cmd_idx == MMC_CMD(13))) {
401 return 0; /* Retry managed by framework */
402 }
403
404 /* Command 8 is expected to fail for eMMC */
Yann Gautierdbb9f572020-06-12 12:17:17 +0200405 if (cmd->cmd_idx != MMC_CMD(8)) {
406 WARN(" CMD%u, Retry: %u, Error: %d\n",
407 cmd->cmd_idx, retry + 1U, err);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200408 }
409
Yann Gautierdbb9f572020-06-12 12:17:17 +0200410 udelay(10U);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200411 }
412
413 return err;
414}
415
416static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
417{
418 uintptr_t base = sdmmc2_params.reg_base;
419 uint32_t bus_cfg = 0;
Yann Gautier3194afe2019-05-28 11:54:50 +0200420 uint32_t clock_div, max_freq, freq;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200421 uint32_t clk_rate = sdmmc2_params.clk_rate;
422 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq;
423
424 switch (width) {
425 case MMC_BUS_WIDTH_1:
426 break;
427 case MMC_BUS_WIDTH_4:
428 bus_cfg |= SDMMC_CLKCR_WIDBUS_4;
429 break;
430 case MMC_BUS_WIDTH_8:
431 bus_cfg |= SDMMC_CLKCR_WIDBUS_8;
432 break;
433 default:
434 panic();
435 break;
436 }
437
438 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
439 if (max_bus_freq >= 52000000U) {
Yann Gautiera2e2a302019-02-14 11:13:39 +0100440 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200441 } else {
Yann Gautiera2e2a302019-02-14 11:13:39 +0100442 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200443 }
444 } else {
445 if (max_bus_freq >= 50000000U) {
Yann Gautiera2e2a302019-02-14 11:13:39 +0100446 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200447 } else {
Yann Gautiera2e2a302019-02-14 11:13:39 +0100448 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200449 }
450 }
451
Yann Gautier3194afe2019-05-28 11:54:50 +0200452 if (sdmmc2_params.max_freq != 0U) {
453 freq = MIN(sdmmc2_params.max_freq, max_freq);
454 } else {
455 freq = max_freq;
456 }
457
458 clock_div = div_round_up(clk_rate, freq * 2U);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200459
460 mmio_write_32(base + SDMMC_CLKCR,
461 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg |
462 sdmmc2_params.negedge |
463 sdmmc2_params.pin_ckin);
464
465 return 0;
466}
467
468static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size)
469{
470 struct mmc_cmd cmd;
471 int ret;
472 uintptr_t base = sdmmc2_params.reg_base;
473 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR;
Yann Gautier6d9e6a02019-06-11 20:03:07 +0200474 uint32_t arg_size;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200475
Yann Gautier6d9e6a02019-06-11 20:03:07 +0200476 assert(size != 0U);
477
478 if (size > MMC_BLOCK_SIZE) {
479 arg_size = MMC_BLOCK_SIZE;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200480 } else {
Yann Gautier6d9e6a02019-06-11 20:03:07 +0200481 arg_size = size;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200482 }
483
484 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf);
485
486 if (sdmmc2_params.use_dma) {
487 inv_dcache_range(buf, size);
488 }
489
490 /* Prepare CMD 16*/
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100491 mmio_write_32(base + SDMMC_DTIMER, 0);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200492
493 mmio_write_32(base + SDMMC_DLENR, 0);
494
Yann Gautier1a3fc9f2019-01-17 14:35:22 +0100495 mmio_write_32(base + SDMMC_DCTRLR, 0);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200496
497 zeromem(&cmd, sizeof(struct mmc_cmd));
498
499 cmd.cmd_idx = MMC_CMD(16);
Yann Gautier6d9e6a02019-06-11 20:03:07 +0200500 cmd.cmd_arg = arg_size;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200501 cmd.resp_type = MMC_RESPONSE_R1;
502
503 ret = stm32_sdmmc2_send_cmd(&cmd);
504 if (ret != 0) {
505 ERROR("CMD16 failed\n");
506 return ret;
507 }
508
509 /* Prepare data command */
510 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
511
512 mmio_write_32(base + SDMMC_DLENR, size);
513
514 if (sdmmc2_params.use_dma) {
515 mmio_write_32(base + SDMMC_IDMACTRLR,
516 SDMMC_IDMACTRLR_IDMAEN);
517 mmio_write_32(base + SDMMC_IDMABASE0R, buf);
518
519 flush_dcache_range(buf, size);
520 }
521
Yann Gautier6d9e6a02019-06-11 20:03:07 +0200522 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT;
523
Yann Gautier5380b0d2018-10-15 09:36:04 +0200524 mmio_clrsetbits_32(base + SDMMC_DCTRLR,
525 SDMMC_DCTRLR_CLEAR_MASK,
526 data_ctrl);
527
528 return 0;
529}
530
531static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
532{
533 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL |
534 SDMMC_STAR_DTIMEOUT;
535 uint32_t flags = error_flags | SDMMC_STAR_DATAEND;
536 uint32_t status;
537 uint32_t *buffer;
538 uintptr_t base = sdmmc2_params.reg_base;
539 uintptr_t fifo_reg = base + SDMMC_FIFOR;
Yann Gautier2299d572019-02-14 11:14:39 +0100540 uint64_t timeout;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200541 int ret;
542
543 /* Assert buf is 4 bytes aligned */
544 assert((buf & GENMASK(1, 0)) == 0U);
545
546 buffer = (uint32_t *)buf;
547
548 if (sdmmc2_params.use_dma) {
549 inv_dcache_range(buf, size);
550
551 return 0;
552 }
553
554 if (size <= MMC_BLOCK_SIZE) {
555 flags |= SDMMC_STAR_DBCKEND;
556 }
557
Yann Gautier2299d572019-02-14 11:14:39 +0100558 timeout = timeout_init_us(TIMEOUT_US_1_S);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200559
560 do {
561 status = mmio_read_32(base + SDMMC_STAR);
562
563 if ((status & error_flags) != 0U) {
564 ERROR("%s: Read error (status = %x)\n", __func__,
565 status);
566 mmio_write_32(base + SDMMC_DCTRLR,
567 SDMMC_DCTRLR_FIFORST);
568
569 mmio_write_32(base + SDMMC_ICR,
570 SDMMC_STATIC_FLAGS);
571
572 ret = stm32_sdmmc2_stop_transfer();
573 if (ret != 0) {
574 return ret;
575 }
576
577 return -EIO;
578 }
579
Yann Gautier2299d572019-02-14 11:14:39 +0100580 if (timeout_elapsed(timeout)) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200581 ERROR("%s: timeout 1s (status = %x)\n",
582 __func__, status);
583 mmio_write_32(base + SDMMC_ICR,
584 SDMMC_STATIC_FLAGS);
585
586 ret = stm32_sdmmc2_stop_transfer();
587 if (ret != 0) {
588 return ret;
589 }
590
591 return -ETIMEDOUT;
592 }
593
594 if (size < (8U * sizeof(uint32_t))) {
595 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) &&
596 ((status & SDMMC_STAR_RXFIFOE) == 0U)) {
597 *buffer = mmio_read_32(fifo_reg);
598 buffer++;
599 }
600 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) {
601 uint32_t count;
602
603 /* Read data from SDMMC Rx FIFO */
604 for (count = 0; count < 8U; count++) {
605 *buffer = mmio_read_32(fifo_reg);
606 buffer++;
607 }
608 }
609 } while ((status & flags) == 0U);
610
611 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
612
613 if ((status & SDMMC_STAR_DPSMACT) != 0U) {
614 WARN("%s: DPSMACT=1, send stop\n", __func__);
615 return stm32_sdmmc2_stop_transfer();
616 }
617
618 return 0;
619}
620
621static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size)
622{
623 return 0;
624}
625
626static int stm32_sdmmc2_dt_get_config(void)
627{
628 int sdmmc_node;
629 void *fdt = NULL;
630 const fdt32_t *cuint;
Yann Gautiere289cb02019-11-04 14:27:23 +0100631 struct dt_node_info dt_info;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200632
633 if (fdt_get_address(&fdt) == 0) {
634 return -FDT_ERR_NOTFOUND;
635 }
636
637 if (fdt == NULL) {
638 return -FDT_ERR_NOTFOUND;
639 }
640
Yann Gautiere289cb02019-11-04 14:27:23 +0100641 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT,
642 sdmmc2_params.reg_base);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200643 if (sdmmc_node == -FDT_ERR_NOTFOUND) {
644 return -FDT_ERR_NOTFOUND;
645 }
646
Yann Gautiere289cb02019-11-04 14:27:23 +0100647 dt_fill_device_info(&dt_info, sdmmc_node);
648 if (dt_info.status == DT_DISABLED) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200649 return -FDT_ERR_NOTFOUND;
650 }
651
652 if (dt_set_pinctrl_config(sdmmc_node) != 0) {
653 return -FDT_ERR_BADVALUE;
654 }
655
Yann Gautiere289cb02019-11-04 14:27:23 +0100656 sdmmc2_params.clock_id = dt_info.clock;
657 sdmmc2_params.reset_id = dt_info.reset;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200658
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100659 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200660 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0;
661 }
662
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100663 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200664 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL;
665 }
666
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100667 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) {
Yann Gautier5380b0d2018-10-15 09:36:04 +0200668 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE;
669 }
670
671 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL);
672 if (cuint != NULL) {
673 switch (fdt32_to_cpu(*cuint)) {
674 case 4:
675 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4;
676 break;
677
678 case 8:
679 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8;
680 break;
681
682 default:
683 break;
684 }
685 }
686
Yann Gautier3194afe2019-05-28 11:54:50 +0200687 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL);
688 if (cuint != NULL) {
689 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint);
690 }
691
Yann Gautier5380b0d2018-10-15 09:36:04 +0200692 return 0;
693}
694
695unsigned long long stm32_sdmmc2_mmc_get_device_size(void)
696{
697 return sdmmc2_params.device_info->device_size;
698}
699
700int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
701{
Etienne Carrieref02647a2019-12-08 08:14:40 +0100702 int rc;
703
Yann Gautier5380b0d2018-10-15 09:36:04 +0200704 assert((params != NULL) &&
705 ((params->reg_base & MMC_BLOCK_MASK) == 0U) &&
706 ((params->bus_width == MMC_BUS_WIDTH_1) ||
707 (params->bus_width == MMC_BUS_WIDTH_4) ||
708 (params->bus_width == MMC_BUS_WIDTH_8)));
709
710 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params));
711
712 if (stm32_sdmmc2_dt_get_config() != 0) {
713 ERROR("%s: DT error\n", __func__);
714 return -ENOMEM;
715 }
716
Yann Gautiere4a3c352019-02-14 10:53:33 +0100717 stm32mp_clk_enable(sdmmc2_params.clock_id);
Yann Gautier5380b0d2018-10-15 09:36:04 +0200718
Etienne Carrieref02647a2019-12-08 08:14:40 +0100719 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
720 if (rc != 0) {
721 panic();
722 }
Yann Gautier5380b0d2018-10-15 09:36:04 +0200723 udelay(2);
Etienne Carrieref02647a2019-12-08 08:14:40 +0100724 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
725 if (rc != 0) {
726 panic();
727 }
Yann Gautier5380b0d2018-10-15 09:36:04 +0200728 mdelay(1);
729
Yann Gautiera2e2a302019-02-14 11:13:39 +0100730 sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);
Yann Gautierc8fa1aa2019-03-08 10:59:00 +0100731 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4;
Yann Gautier5380b0d2018-10-15 09:36:04 +0200732
733 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
734 sdmmc2_params.bus_width, sdmmc2_params.flags,
735 sdmmc2_params.device_info);
736}