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Antonio Nino Diazc326c342019-01-11 11:20:10 +00001/*
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06002 * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
Antonio Nino Diazc326c342019-01-11 11:20:10 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef ARCH_FEATURES_H
8#define ARCH_FEATURES_H
9
10#include <stdbool.h>
11
12#include <arch_helpers.h>
Andre Przywarae8920f62022-11-10 14:28:01 +000013#include <common/feat_detect.h>
Antonio Nino Diazc326c342019-01-11 11:20:10 +000014
Andre Przywarabb0db3b2023-01-25 12:26:14 +000015#define ISOLATE_FIELD(reg, feat) \
Andre Przywara0dda4242023-04-18 16:58:36 +010016 ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
Andre Przywarabb0db3b2023-01-25 12:26:14 +000017
Andre Przywara0dda4242023-04-18 16:58:36 +010018#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
19static inline bool is_ ## name ## _supported(void) \
20{ \
21 if ((guard) == FEAT_STATE_DISABLED) { \
22 return false; \
23 } \
24 if ((guard) == FEAT_STATE_ALWAYS) { \
25 return true; \
26 } \
27 return read_func() >= (idvalue); \
Antonio Nino Diazd29d21e2019-02-06 09:23:04 +000028}
29
Andre Przywara0dda4242023-04-18 16:58:36 +010030#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
31static unsigned int read_ ## name ## _id_field(void) \
32{ \
33 return ISOLATE_FIELD(read_ ## idreg(), idfield); \
34} \
35CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
Andre Przywara97272942023-01-26 15:27:38 +000036
Andre Przywara0dda4242023-04-18 16:58:36 +010037static inline bool is_armv7_gentimer_present(void)
Andre Przywara98908b32022-11-17 16:42:09 +000038{
Andre Przywara0dda4242023-04-18 16:58:36 +010039 /* The Generic Timer is always present in an ARMv8-A implementation */
40 return true;
Andre Przywara98908b32022-11-17 16:42:09 +000041}
42
Andre Przywara0dda4242023-04-18 16:58:36 +010043CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
44 ENABLE_FEAT_PAN)
Manish Pandey5cfe5152024-01-09 15:55:20 +000045static inline bool is_feat_pan_present(void)
46{
47 return read_feat_pan_id_field() != 0U;
48}
49
Andre Przywara0dda4242023-04-18 16:58:36 +010050CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
51 ENABLE_FEAT_VHE)
Daniel Boulby44b43332020-11-25 16:36:46 +000052
Antonio Nino Diazc326c342019-01-11 11:20:10 +000053static inline bool is_armv8_2_ttcnp_present(void)
54{
55 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
56 ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
57}
58
Manish Pandey5cfe5152024-01-09 15:55:20 +000059static inline bool is_feat_uao_present(void)
60{
61 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_UAO_SHIFT) &
62 ID_AA64MMFR2_EL1_UAO_MASK) != 0U;
63}
64
Juan Pablo Condee089a172022-06-29 17:44:43 -040065static inline bool is_feat_pacqarma3_present(void)
66{
67 uint64_t mask_id_aa64isar2 =
68 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
69 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT);
70
71 /* If any of the fields is not zero, QARMA3 algorithm is present */
72 return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U;
73}
74
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000075static inline bool is_armv8_3_pauth_present(void)
76{
Juan Pablo Condee089a172022-06-29 17:44:43 -040077 uint64_t mask_id_aa64isar1 =
78 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
79 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) |
80 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
81 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000082
Juan Pablo Condee089a172022-06-29 17:44:43 -040083 /*
84 * If any of the fields is not zero or QARMA3 is present,
85 * PAuth is present
86 */
87 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U ||
88 is_feat_pacqarma3_present());
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000089}
90
Sathees Balya74155972019-01-25 11:36:01 +000091static inline bool is_armv8_4_ttst_present(void)
92{
93 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
94 ID_AA64MMFR2_EL1_ST_MASK) == 1U;
95}
96
Alexei Fedorov90f2e882019-05-24 12:17:09 +010097static inline bool is_armv8_5_bti_present(void)
98{
99 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
100 ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
101}
102
Manish Pandey5cfe5152024-01-09 15:55:20 +0000103static inline unsigned int get_armv8_5_mte_support(void)
104{
105 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
106 ID_AA64PFR1_EL1_MTE_MASK);
107}
108
109static inline bool is_feat_ssbs_present(void)
110{
111 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
112 ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_UNAVAILABLE;
113}
114
115static inline bool is_feat_nmi_present(void)
116{
117 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_NMI_SHIFT) &
118 ID_AA64PFR1_EL1_NMI_MASK) == NMI_IMPLEMENTED;
119}
120
121static inline bool is_feat_gcs_present(void)
122{
123 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_GCS_SHIFT) &
124 ID_AA64PFR1_EL1_GCS_MASK) == GCS_IMPLEMENTED;
125}
126
127static inline bool is_feat_ebep_present(void)
128{
129 return ((read_id_aa64dfr1_el1() >> ID_AA64DFR1_EBEP_SHIFT) &
130 ID_AA64DFR1_EBEP_MASK) == EBEP_IMPLEMENTED;
131}
132
133static inline bool is_feat_sebep_present(void)
134{
135 return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_SEBEP_SHIFT) &
136 ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
137}
138
Govindraj Raja24d3a4e2023-12-21 13:57:49 -0600139CREATE_FEATURE_FUNCS(feat_mte, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
140 ENABLE_FEAT_MTE)
Govindraj Rajad7b63ac2024-01-26 10:08:37 -0600141CREATE_FEATURE_FUNCS_VER(feat_mte2, read_feat_mte_id_field, MTE_IMPLEMENTED_ELX,
142 ENABLE_FEAT_MTE2)
Andre Przywara0dda4242023-04-18 16:58:36 +0100143CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
144 ENABLE_FEAT_SEL2)
145CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
146 ENABLE_FEAT_TWED)
147CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
148 ENABLE_FEAT_FGT)
149CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
150 ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
151CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
152 ENABLE_FEAT_ECV)
153CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
154 ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
Mark Brownc37eee72023-03-14 20:13:03 +0000155
Andre Przywara0dda4242023-04-18 16:58:36 +0100156CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
157 ENABLE_FEAT_RNG)
158CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
159 ENABLE_FEAT_TCR2)
Mark Brown293a6612023-03-14 20:48:43 +0000160
Andre Przywara0dda4242023-04-18 16:58:36 +0100161CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
162 ENABLE_FEAT_S2POE)
163CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
164 ENABLE_FEAT_S1POE)
Mark Brown293a6612023-03-14 20:48:43 +0000165static inline bool is_feat_sxpoe_supported(void)
166{
167 return is_feat_s1poe_supported() || is_feat_s2poe_supported();
168}
169
Andre Przywara0dda4242023-04-18 16:58:36 +0100170CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
171 ENABLE_FEAT_S2PIE)
172CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
173 ENABLE_FEAT_S1PIE)
Mark Brown293a6612023-03-14 20:48:43 +0000174static inline bool is_feat_sxpie_supported(void)
175{
176 return is_feat_s1pie_supported() || is_feat_s2pie_supported();
177}
178
Andre Przywara0dda4242023-04-18 16:58:36 +0100179/* FEAT_GCS: Guarded Control Stack */
180CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
181 ENABLE_FEAT_GCS)
Andre Przywara2c550e32022-11-10 14:41:07 +0000182
Andre Przywara0dda4242023-04-18 16:58:36 +0100183/* FEAT_AMU: Activity Monitors Extension */
184CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
185 ENABLE_FEAT_AMU)
186CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
187 ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
johpow01fa59c6f2020-10-02 13:41:11 -0500188
Alexei Fedorov19933552020-05-26 13:16:41 +0100189/*
190 * Return MPAM version:
191 *
192 * 0x00: None Armv8.0 or later
193 * 0x01: v0.1 Armv8.4 or later
194 * 0x10: v1.0 Armv8.2 or later
195 * 0x11: v1.1 Armv8.4 or later
196 *
197 */
Andre Przywara84b86532022-11-17 16:42:09 +0000198static inline unsigned int read_feat_mpam_version(void)
Alexei Fedorov19933552020-05-26 13:16:41 +0100199{
200 return (unsigned int)((((read_id_aa64pfr0_el1() >>
201 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
202 ((read_id_aa64pfr1_el1() >>
203 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
204}
205
Andre Przywara0dda4242023-04-18 16:58:36 +0100206CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
Arvind Ram Prakashab28d4b2023-10-11 12:10:56 -0500207 ENABLE_FEAT_MPAM)
Andre Przywaraf20ad902022-11-15 11:45:19 +0000208
Andre Przywara0dda4242023-04-18 16:58:36 +0100209/* FEAT_HCX: Extended Hypervisor Configuration Register */
210CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
211 ENABLE_FEAT_HCX)
johpow01f91e59f2021-08-04 19:38:18 -0500212
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400213static inline bool is_feat_rng_trap_present(void)
214{
215 return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
216 ID_AA64PFR1_EL1_RNDR_TRAP_MASK)
217 == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED);
218}
219
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500220static inline unsigned int get_armv9_2_feat_rme_support(void)
221{
222 /*
223 * Return the RME version, zero if not supported. This function can be
224 * used as both an integer value for the RME version or compared to zero
225 * to detect RME presence.
226 */
227 return (unsigned int)(read_id_aa64pfr0_el1() >>
228 ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
229}
230
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000231/*********************************************************************************
232 * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
233 ********************************************************************************/
Andre Przywara46880dc2022-11-17 16:42:09 +0000234static inline unsigned int read_feat_sb_id_field(void)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000235{
Andre Przywara0dda4242023-04-18 16:58:36 +0100236 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
Andre Przywara06ea44e2022-11-17 17:30:43 +0000237}
238
Sona Mathew3b84c962023-10-25 16:48:19 -0500239/*
240 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59]
241 * of id_aa64pfr0_el1 register and can be used to check for below features:
242 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2.
243 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3.
244 * 0b0000 - Feature FEAT_CSV2 is not implemented.
245 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3
246 * are not implemented.
247 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not
248 * implemented.
249 * 0b0011 - Feature FEAT_CSV2_3 is implemented.
250 */
251static inline unsigned int read_feat_csv2_id_field(void)
252{
253 return (unsigned int)(read_id_aa64pfr0_el1() >>
254 ID_AA64PFR0_CSV2_SHIFT) & ID_AA64PFR0_CSV2_MASK;
255}
256
Andre Przywara0dda4242023-04-18 16:58:36 +0100257CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
258 ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
Sona Mathew3b84c962023-10-25 16:48:19 -0500259CREATE_FEATURE_FUNCS_VER(feat_csv2_3, read_feat_csv2_id_field,
260 ID_AA64PFR0_CSV2_3_SUPPORTED, ENABLE_FEAT_CSV2_3)
Andre Przywara06ea44e2022-11-17 17:30:43 +0000261
Andre Przywara0dda4242023-04-18 16:58:36 +0100262/* FEAT_SPE: Statistical Profiling Extension */
263CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
264 ENABLE_SPE_FOR_NS)
Andre Przywara06ea44e2022-11-17 17:30:43 +0000265
Andre Przywara0dda4242023-04-18 16:58:36 +0100266/* FEAT_SVE: Scalable Vector Extension */
267CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
268 ENABLE_SVE_FOR_NS)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000269
Andre Przywara0dda4242023-04-18 16:58:36 +0100270/* FEAT_RAS: Reliability, Accessibility, Serviceability */
271CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
272 ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000273
Andre Przywara0dda4242023-04-18 16:58:36 +0100274/* FEAT_DIT: Data Independent Timing instructions */
275CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
276 ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000277
Andre Przywara0dda4242023-04-18 16:58:36 +0100278CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
279 ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000280
Andre Przywara0dda4242023-04-18 16:58:36 +0100281/* FEAT_TRF: TraceFilter */
282CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
283 ENABLE_TRF_FOR_NS)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000284
Andre Przywara0dda4242023-04-18 16:58:36 +0100285/* FEAT_NV2: Enhanced Nested Virtualization */
286CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
287CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
288 ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000289
Andre Przywara0dda4242023-04-18 16:58:36 +0100290/* FEAT_BRBE: Branch Record Buffer Extension */
291CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
292 ENABLE_BRBE_FOR_NS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000293
Andre Przywara0dda4242023-04-18 16:58:36 +0100294/* FEAT_TRBE: Trace Buffer Extension */
295CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
296 ENABLE_TRBE_FOR_NS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000297
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000298static inline unsigned int read_feat_sme_fa64_id_field(void)
299{
Andre Przywara0dda4242023-04-18 16:58:36 +0100300 return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
301 ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000302}
Andre Przywara0dda4242023-04-18 16:58:36 +0100303/* FEAT_SMEx: Scalar Matrix Extension */
304CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
305 ENABLE_SME_FOR_NS)
306CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
307 ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000308
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100309/*******************************************************************************
310 * Function to get hardware granularity support
311 ******************************************************************************/
312
313static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
314{
Andre Przywara0dda4242023-04-18 16:58:36 +0100315 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
316 ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100317}
318
319static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
320{
321 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
Andre Przywara0dda4242023-04-18 16:58:36 +0100322 ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100323}
324
325static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
326{
327 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
Andre Przywara0dda4242023-04-18 16:58:36 +0100328 ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100329}
330
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000331static inline unsigned int read_feat_pmuv3_id_field(void)
332{
Andre Przywara0dda4242023-04-18 16:58:36 +0100333 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000334}
335
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000336static inline unsigned int read_feat_mtpmu_id_field(void)
337{
Andre Przywara0dda4242023-04-18 16:58:36 +0100338 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000339}
340
341static inline bool is_feat_mtpmu_supported(void)
342{
343 if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
344 return false;
345 }
346
347 if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
348 return true;
349 }
350
351 unsigned int mtpmu = read_feat_mtpmu_id_field();
352
353 return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED);
354}
355
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000356#endif /* ARCH_FEATURES_H */