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Chandni Cherukuria3f66132018-08-10 11:17:58 +05301/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
11
Chandni Cherukuria3f66132018-08-10 11:17:58 +053012#include <sgi_base_platform_def.h>
13
14#define PLAT_ARM_CLUSTER_COUNT 2
15#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
16#define CSS_SGI_MAX_PE_PER_CPU 1
17
Vijayenthiran Subramaniam22141b62018-10-25 22:20:24 +053018#define PLAT_CSS_MHU_BASE UL(0x45000000)
Masahisa Kojima0d316882019-03-07 11:23:42 +090019#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
Vijayenthiran Subramaniam22141b62018-10-25 22:20:24 +053020
21/* Base address of DMC-620 instances */
22#define SGI575_DMC620_BASE0 UL(0x4e000000)
23#define SGI575_DMC620_BASE1 UL(0x4e100000)
Chandni Cherukuria3f66132018-08-10 11:17:58 +053024
Chandni Cherukuri0fdcbc02018-10-16 15:19:54 +053025/* System power domain level */
26#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
27
Chandni Cherukuri504c05d2018-10-16 14:11:34 +053028#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
29
Manoj Kumar69bebd82019-06-21 17:07:13 +010030/*
31 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
32 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -070033#ifdef __aarch64__
Manoj Kumar69bebd82019-06-21 17:07:13 +010034#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
35#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
36#else
37#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
38#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
39#endif
40
Chandni Cherukuria3f66132018-08-10 11:17:58 +053041#endif /* PLATFORM_DEF_H */