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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew47e43f22016-02-01 14:04:34 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2b6b5742015-03-19 19:17:53 +00007#include <arch.h>
Soby Mathew47e43f22016-02-01 14:04:34 +00008#include <cassert.h>
Soby Mathewfec4eb72015-07-01 16:16:20 +01009#include <plat_arm.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010010#include <platform_def.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010011#include "drivers/pwrc/fvp_pwrc.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
Soby Mathewfec4eb72015-07-01 16:16:20 +010013/* The FVP power domain tree descriptor */
Soby Mathew47e43f22016-02-01 14:04:34 +000014unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 1];
15
16
17CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count);
18
19/*******************************************************************************
20 * This function dynamically constructs the topology according to
21 * FVP_CLUSTER_COUNT and returns it.
22 ******************************************************************************/
23const unsigned char *plat_get_power_domain_tree_desc(void)
24{
25 int i;
26
27 /*
28 * The FVP power domain tree does not have a single system level power domain
29 * i.e. a single root node. The first entry in the power domain descriptor
30 * specifies the number of power domains at the highest power level. For the FVP
31 * this is the number of cluster power domains.
32 */
33 fvp_power_domain_tree_desc[0] = FVP_CLUSTER_COUNT;
34
35 for (i = 0; i < FVP_CLUSTER_COUNT; i++)
36 fvp_power_domain_tree_desc[i + 1] = FVP_MAX_CPUS_PER_CLUSTER;
37
38 return fvp_power_domain_tree_desc;
39}
40
41/*******************************************************************************
42 * This function returns the core count within the cluster corresponding to
43 * `mpidr`.
44 ******************************************************************************/
45unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
46{
47 return FVP_MAX_CPUS_PER_CLUSTER;
48}
Achin Gupta4f6ad662013-10-25 09:08:21 +010049
50/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 * This function implements a part of the critical interface between the psci
Soby Mathewfec4eb72015-07-01 16:16:20 +010052 * generic layer and the platform that allows the former to query the platform
53 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
54 * in case the MPIDR is invalid.
Achin Gupta4f6ad662013-10-25 09:08:21 +010055 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010056int plat_core_pos_by_mpidr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010057{
Soby Mathewfec4eb72015-07-01 16:16:20 +010058 if (arm_check_mpidr(mpidr) == -1)
59 return -1;
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Soby Mathewfec4eb72015-07-01 16:16:20 +010061 if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID)
62 return -1;
Achin Gupta4f6ad662013-10-25 09:08:21 +010063
Soby Mathewfec4eb72015-07-01 16:16:20 +010064 return plat_arm_calc_core_pos(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +010065}