blob: 009ee640367207880bba0a5e946b6b7601b01700 [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arm_def.h>
8#include <bl_common.h>
9#include <debug.h>
10#include <plat_arm.h>
11#include <platform_def.h>
12#include <sgm_variant.h>
13
14/*
15 * Table of regions for different BL stages to map using the MMU.
16 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
17 * arm_configure_mmu_elx() will give the available subset of that.
18 */
19#if IMAGE_BL1
20const mmap_region_t plat_arm_mmap[] = {
21 ARM_MAP_SHARED_RAM,
22 V2M_MAP_FLASH0_RO,
23 V2M_MAP_IOFPGA,
24 CSS_MAP_DEVICE,
25 CSS_MAP_GIC_DEVICE,
26 SOC_CSS_MAP_DEVICE,
27#if TRUSTED_BOARD_BOOT
28 ARM_MAP_NS_DRAM1,
29#endif
30 {0}
31};
32#endif
33#if IMAGE_BL2
34const mmap_region_t plat_arm_mmap[] = {
35 ARM_MAP_SHARED_RAM,
36 V2M_MAP_FLASH0_RO,
37 V2M_MAP_IOFPGA,
38 CSS_MAP_DEVICE,
39 CSS_MAP_GIC_DEVICE,
40 SOC_CSS_MAP_DEVICE,
41 ARM_MAP_NS_DRAM1,
42 ARM_MAP_TSP_SEC_MEM,
43#ifdef SPD_opteed
44 ARM_OPTEE_PAGEABLE_LOAD_MEM,
45#endif
46 {0}
47};
48#endif
49#if IMAGE_BL2U
50const mmap_region_t plat_arm_mmap[] = {
51 ARM_MAP_SHARED_RAM,
52 CSS_MAP_DEVICE,
53 CSS_MAP_GIC_DEVICE,
54 SOC_CSS_MAP_DEVICE,
55 {0}
56};
57#endif
58#if IMAGE_BL31
59const mmap_region_t plat_arm_mmap[] = {
60 ARM_MAP_SHARED_RAM,
61 V2M_MAP_IOFPGA,
62 CSS_MAP_DEVICE,
63 CSS_MAP_GIC_DEVICE,
64 SOC_CSS_MAP_DEVICE,
65 {0}
66};
67#endif
68#if IMAGE_BL32
69const mmap_region_t plat_arm_mmap[] = {
70 V2M_MAP_IOFPGA,
71 CSS_MAP_DEVICE,
72 CSS_MAP_GIC_DEVICE,
73 SOC_CSS_MAP_DEVICE,
74 {0}
75};
76#endif
77
78ARM_CASSERT_MMAP
79
80const mmap_region_t *plat_arm_get_mmap(void)
81{
82 return plat_arm_mmap;
83}