Blame - bl32/tsp/aarch64/tsp_exceptions.S - filogic/atf

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Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	1	/*
Antonio Nino Diaz	1f21bcf	2016-02-01 13:57:25 +0000	[diff] [blame]	2	* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	3	*
dp-arm	fa3cf0b	2017-05-03 09:38:09 +0100	[diff] [blame]	4	* SPDX-License-Identifier: BSD-3-Clause
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	5	*/
				6
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	7	#include <arch.h>
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	8	#include <asm_macros.S>
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	9	#include <bl_common.h>
				10	#include <tsp.h>
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	11
				12
				13	/* ----------------------------------------------------
				14	* The caller-saved registers x0-x18 and LR are saved
				15	* here.
				16	* ----------------------------------------------------
				17	*/
				18
				19	#define SCRATCH_REG_SIZE #(20 * 8)
				20
				21	.macro save_caller_regs_and_lr
				22	sub sp, sp, SCRATCH_REG_SIZE
				23	stp x0, x1, [sp]
				24	stp x2, x3, [sp, #0x10]
				25	stp x4, x5, [sp, #0x20]
				26	stp x6, x7, [sp, #0x30]
				27	stp x8, x9, [sp, #0x40]
				28	stp x10, x11, [sp, #0x50]
				29	stp x12, x13, [sp, #0x60]
				30	stp x14, x15, [sp, #0x70]
				31	stp x16, x17, [sp, #0x80]
				32	stp x18, x30, [sp, #0x90]
				33	.endm
				34
				35	.macro restore_caller_regs_and_lr
				36	ldp x0, x1, [sp]
				37	ldp x2, x3, [sp, #0x10]
				38	ldp x4, x5, [sp, #0x20]
				39	ldp x6, x7, [sp, #0x30]
				40	ldp x8, x9, [sp, #0x40]
				41	ldp x10, x11, [sp, #0x50]
				42	ldp x12, x13, [sp, #0x60]
				43	ldp x14, x15, [sp, #0x70]
				44	ldp x16, x17, [sp, #0x80]
				45	ldp x18, x30, [sp, #0x90]
				46	add sp, sp, SCRATCH_REG_SIZE
				47	.endm
				48
Soby Mathew	bec9851	2015-09-03 18:29:38 +0100	[diff] [blame]	49	/* ----------------------------------------------------
				50	* Common TSP interrupt handling routine
				51	* ----------------------------------------------------
				52	*/
				53	.macro handle_tsp_interrupt label
				54	/* Enable the SError interrupt */
				55	msr daifclr, #DAIF_ABT_BIT
				56
				57	save_caller_regs_and_lr
				58	bl tsp_common_int_handler
				59	cbz x0, interrupt_exit_\label
				60
				61	/*
				62	* This interrupt was not targetted to S-EL1 so send it to
				63	* the monitor and wait for execution to resume.
				64	*/
				65	smc #0
				66	interrupt_exit_\label:
				67	restore_caller_regs_and_lr
				68	eret
				69	.endm
				70
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	71	.globl tsp_exceptions
				72
				73	/* -----------------------------------------------------
				74	* TSP exception handlers.
				75	* -----------------------------------------------------
				76	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	77	vector_base tsp_exceptions
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	78	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	79	* Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	80	* are expected and treated as irrecoverable errors.
				81	* -----------------------------------------------------
				82	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	83	vector_entry sync_exception_sp_el0
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	84	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	85	end_vector_entry sync_exception_sp_el0
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	86
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	87	vector_entry irq_sp_el0
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	88	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	89	end_vector_entry irq_sp_el0
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	90
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	91	vector_entry fiq_sp_el0
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	92	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	93	end_vector_entry fiq_sp_el0
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	94
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	95	vector_entry serror_sp_el0
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	96	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	97	end_vector_entry serror_sp_el0
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	98
				99
				100	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	101	* Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	102	* are expected and handled
				103	* -----------------------------------------------------
				104	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	105	vector_entry sync_exception_sp_elx
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	106	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	107	end_vector_entry sync_exception_sp_elx
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	108
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	109	vector_entry irq_sp_elx
Soby Mathew	bec9851	2015-09-03 18:29:38 +0100	[diff] [blame]	110	handle_tsp_interrupt irq_sp_elx
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	111	end_vector_entry irq_sp_elx
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	112
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	113	vector_entry fiq_sp_elx
Soby Mathew	bec9851	2015-09-03 18:29:38 +0100	[diff] [blame]	114	handle_tsp_interrupt fiq_sp_elx
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	115	end_vector_entry fiq_sp_elx
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	116
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	117	vector_entry serror_sp_elx
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	118	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	119	end_vector_entry serror_sp_elx
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	120
				121
				122	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	123	* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	124	* are handled since TSP does not implement a lower EL
				125	* -----------------------------------------------------
				126	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	127	vector_entry sync_exception_aarch64
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	128	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	129	end_vector_entry sync_exception_aarch64
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	130
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	131	vector_entry irq_aarch64
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	132	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	133	end_vector_entry irq_aarch64
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	134
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	135	vector_entry fiq_aarch64
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	136	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	137	end_vector_entry fiq_aarch64
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	138
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	139	vector_entry serror_aarch64
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	140	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	141	end_vector_entry serror_aarch64
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	142
				143
				144	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	145	* Lower EL using AArch32 : 0x600 - 0x800. No exceptions
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	146	* handled since the TSP does not implement a lower EL.
				147	* -----------------------------------------------------
				148	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	149	vector_entry sync_exception_aarch32
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	150	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	151	end_vector_entry sync_exception_aarch32
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	152
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	153	vector_entry irq_aarch32
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	154	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	155	end_vector_entry irq_aarch32
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	156
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	157	vector_entry fiq_aarch32
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	158	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	159	end_vector_entry fiq_aarch32
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	160
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	161	vector_entry serror_aarch32
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	162	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	163	end_vector_entry serror_aarch32