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git01.mediatek.com / filogic / atf / 988bbb22a3d7543e15b3f7284a3e25a4a7547a67 / . / fdts / stm32mp15-pinctrl.dtsi
blob: d3d1744ec4e77df29d6fc3b1552652ca2d52dd68 [file] [log] [blame]
Yann Gautier4ede20a2020-09-18 15:04:14 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
9 fmc_pins_a: fmc-0 {
10 pins1 {
11 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
12 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
13 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
14 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
15 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
16 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
17 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
18 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
19 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
20 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
21 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
22 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
23 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
24 bias-disable;
25 drive-push-pull;
26 slew-rate = <1>;
27 };
28 pins2 {
29 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
30 bias-pull-up;
31 };
32 };
33
34 qspi_clk_pins_a: qspi-clk-0 {
35 pins {
36 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
37 bias-disable;
38 drive-push-pull;
39 slew-rate = <3>;
40 };
41 };
42
43 qspi_bk1_pins_a: qspi-bk1-0 {
44 pins1 {
45 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
46 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
47 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
48 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
49 bias-disable;
50 drive-push-pull;
51 slew-rate = <1>;
52 };
53 pins2 {
54 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
55 bias-pull-up;
56 drive-push-pull;
57 slew-rate = <1>;
58 };
59 };
60
61 qspi_bk2_pins_a: qspi-bk2-0 {
62 pins1 {
63 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
64 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
65 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
66 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
67 bias-disable;
68 drive-push-pull;
69 slew-rate = <1>;
70 };
71 pins2 {
72 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
73 bias-pull-up;
74 drive-push-pull;
75 slew-rate = <1>;
76 };
77 };
78
79 rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
80 pins {
81 pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
82 };
83 };
84
85 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
86 pins1 {
87 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
88 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
89 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
90 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
91 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
92 slew-rate = <1>;
93 drive-push-pull;
94 bias-disable;
95 };
96 pins2 {
97 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
98 slew-rate = <2>;
99 drive-push-pull;
100 bias-disable;
101 };
102 };
103
104 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
105 pins1 {
106 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
107 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
108 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
109 slew-rate = <1>;
110 drive-push-pull;
111 bias-pull-up;
112 };
113 pins2{
114 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
115 bias-pull-up;
116 };
117 };
118
119 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
120 pins1 {
121 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
122 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
123 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
124 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
125 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
126 slew-rate = <1>;
127 drive-push-pull;
128 bias-pull-up;
129 };
130 pins2 {
131 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
132 slew-rate = <2>;
133 drive-push-pull;
134 bias-pull-up;
135 };
136 };
137
138 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
139 pins1 {
140 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
141 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
142 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
143 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
144 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
145 slew-rate = <1>;
146 drive-push-pull;
147 bias-disable;
148 };
149 pins2 {
150 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
151 slew-rate = <2>;
152 drive-push-pull;
153 bias-disable;
154 };
155 };
156
157 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
158 pins {
159 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
160 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
161 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
162 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
163 slew-rate = <1>;
164 drive-push-pull;
165 bias-pull-up;
166 };
167 };
168
169 uart4_pins_a: uart4-0 {
170 pins1 {
171 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
172 bias-disable;
173 drive-push-pull;
174 slew-rate = <0>;
175 };
176 pins2 {
177 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
178 bias-disable;
179 };
180 };
181
182 uart4_pins_b: uart4-1 {
183 pins1 {
184 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
185 bias-disable;
186 drive-push-pull;
187 slew-rate = <0>;
188 };
189 pins2 {
190 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
191 bias-disable;
192 };
193 };
194
195 uart7_pins_a: uart7-0 {
196 pins1 {
197 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
198 bias-disable;
199 drive-push-pull;
200 slew-rate = <0>;
201 };
202 pins2 {
203 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
204 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
205 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
206 bias-disable;
207 };
208 };
209
210 uart7_pins_b: uart7-1 {
211 pins1 {
212 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
213 bias-disable;
214 drive-push-pull;
215 slew-rate = <0>;
216 };
217 pins2 {
218 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
219 bias-disable;
220 };
221 };
222
223 usart2_pins_a: usart2-0 {
224 pins1 {
225 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
226 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
227 bias-disable;
228 drive-push-pull;
229 slew-rate = <3>;
230 };
231 pins2 {
232 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
233 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
234 bias-disable;
235 };
236 };
237
238 usart3_pins_a: usart3-0 {
239 pins1 {
240 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
241 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
242 bias-disable;
243 drive-push-pull;
244 slew-rate = <0>;
245 };
246 pins2 {
247 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
248 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
249 bias-disable;
250 };
251 };
252
253 usart3_pins_b: usart3-1 {
254 pins1 {
255 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
256 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
257 bias-disable;
258 drive-push-pull;
259 slew-rate = <0>;
260 };
261 pins2 {
262 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
263 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
264 bias-disable;
265 };
266 };
267
268 usbotg_hs_pins_a: usbotg_hs-0 {
269 pins {
270 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
271 };
272 };
273
274 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
275 pins {
276 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
277 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
278 };
279 };
280};
281
282&pinctrl_z {
283 i2c4_pins_a: i2c4-0 {
284 pins {
285 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
286 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
287 bias-disable;
288 drive-open-drain;
289 slew-rate = <0>;
290 };
291 };
292};