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Manish V Badarkhe51a97112021-07-08 09:33:18 +01001/*
Boyan Karatotev6468d4a2023-02-16 15:12:45 +00002 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
Manish V Badarkhe51a97112021-07-08 09:33:18 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Manish V Badarkhe51a97112021-07-08 09:33:18 +01007#include <arch.h>
Andre Przywara06ea44e2022-11-17 17:30:43 +00008#include <arch_features.h>
Manish V Badarkhe51a97112021-07-08 09:33:18 +01009#include <arch_helpers.h>
10#include <lib/extensions/trf.h>
11
Boyan Karatotev6468d4a2023-02-16 15:12:45 +000012void trf_init_el3(void)
Manish V Badarkhe51a97112021-07-08 09:33:18 +010013{
Boyan Karatotev6468d4a2023-02-16 15:12:45 +000014 u_register_t val;
Manish V Badarkhe51a97112021-07-08 09:33:18 +010015
Andre Przywara06ea44e2022-11-17 17:30:43 +000016 /*
17 * MDCR_EL3.TTRF = b0
18 * Allow access of trace filter control registers from NS-EL2
19 * and NS-EL1 when NS-EL2 is implemented but not used
20 */
21 val = read_mdcr_el3();
22 val &= ~MDCR_TTRF_BIT;
23 write_mdcr_el3(val);
Manish V Badarkhe51a97112021-07-08 09:33:18 +010024}
Boyan Karatotev6468d4a2023-02-16 15:12:45 +000025
26void trf_init_el2_unused(void)
27{
28 /*
29 * MDCR_EL2.TTRF: Set to zero so that access to Trace
30 * Filter Control register TRFCR_EL1 at EL1 is not
31 * trapped to EL2. This bit is RES0 in versions of
32 * the architecture earlier than ARMv8.4.
33 *
34 */
35 write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_TTRF);
36}