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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Antonio Nino Diazac998032017-02-27 17:23:54 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
7#ifndef __ARCH_H__
8#define __ARCH_H__
9
10/*******************************************************************************
11 * MIDR bit definitions
12 ******************************************************************************/
13#define MIDR_IMPL_MASK 0xff
14#define MIDR_IMPL_SHIFT 24
15#define MIDR_VAR_SHIFT 20
16#define MIDR_VAR_BITS 4
17#define MIDR_REV_SHIFT 0
18#define MIDR_REV_BITS 4
19#define MIDR_PN_MASK 0xfff
20#define MIDR_PN_SHIFT 4
21
22/*******************************************************************************
23 * MPIDR macros
24 ******************************************************************************/
Summer Qin93c812f2017-02-28 16:46:17 +000025#define MPIDR_MT_MASK (1 << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +010026#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
27#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
28#define MPIDR_AFFINITY_BITS 8
29#define MPIDR_AFFLVL_MASK 0xff
30#define MPIDR_AFFLVL_SHIFT 3
31#define MPIDR_AFF0_SHIFT 0
32#define MPIDR_AFF1_SHIFT 8
33#define MPIDR_AFF2_SHIFT 16
34#define MPIDR_AFFINITY_MASK 0x00ffffff
35#define MPIDR_AFFLVL0 0
36#define MPIDR_AFFLVL1 1
37#define MPIDR_AFFLVL2 2
38
39#define MPIDR_AFFLVL0_VAL(mpidr) \
40 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
41#define MPIDR_AFFLVL1_VAL(mpidr) \
42 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
43#define MPIDR_AFFLVL2_VAL(mpidr) \
44 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
45
46/*
47 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
48 * add one while using this macro to define array sizes.
49 */
50#define MPIDR_MAX_AFFLVL 2
51
52/* Data Cache set/way op type defines */
53#define DC_OP_ISW 0x0
54#define DC_OP_CISW 0x1
55#define DC_OP_CSW 0x2
56
57/*******************************************************************************
58 * Generic timer memory mapped registers & offsets
59 ******************************************************************************/
60#define CNTCR_OFF 0x000
61#define CNTFID_OFF 0x020
62
63#define CNTCR_EN (1 << 0)
64#define CNTCR_HDBG (1 << 1)
65#define CNTCR_FCREQ(x) ((x) << 8)
66
67/*******************************************************************************
68 * System register bit definitions
69 ******************************************************************************/
70/* CLIDR definitions */
71#define LOUIS_SHIFT 21
72#define LOC_SHIFT 24
73#define CLIDR_FIELD_WIDTH 3
74
75/* CSSELR definitions */
76#define LEVEL_SHIFT 1
77
78/* ID_PFR1 definitions */
79#define ID_PFR1_VIRTEXT_SHIFT 12
80#define ID_PFR1_VIRTEXT_MASK 0xf
81#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
82 & ID_PFR1_VIRTEXT_MASK)
83#define ID_PFR1_GIC_SHIFT 28
84#define ID_PFR1_GIC_MASK 0xf
85
86/* SCTLR definitions */
87#define SCTLR_RES1 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \
Soby Mathewa993c422016-09-29 14:15:57 +010088 (1 << 3))
Soby Mathewc6820d12016-05-09 17:49:55 +010089#define SCTLR_M_BIT (1 << 0)
90#define SCTLR_A_BIT (1 << 1)
91#define SCTLR_C_BIT (1 << 2)
92#define SCTLR_CP15BEN_BIT (1 << 5)
93#define SCTLR_ITD_BIT (1 << 7)
94#define SCTLR_I_BIT (1 << 12)
95#define SCTLR_V_BIT (1 << 13)
96#define SCTLR_NTWI_BIT (1 << 16)
97#define SCTLR_NTWE_BIT (1 << 18)
98#define SCTLR_WXN_BIT (1 << 19)
99#define SCTLR_UWXN_BIT (1 << 20)
100#define SCTLR_EE_BIT (1 << 25)
101#define SCTLR_TRE_BIT (1 << 28)
102#define SCTLR_AFE_BIT (1 << 29)
103#define SCTLR_TE_BIT (1 << 30)
David Cunadofee86532017-04-13 22:38:29 +0100104#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
105 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
Soby Mathewc6820d12016-05-09 17:49:55 +0100106
dp-arm595d0d52017-02-08 11:51:50 +0000107/* SDCR definitions */
108#define SDCR_SPD(x) ((x) << 14)
109#define SDCR_SPD_LEGACY 0x0
110#define SDCR_SPD_DISABLE 0x2
111#define SDCR_SPD_ENABLE 0x3
David Cunadofee86532017-04-13 22:38:29 +0100112#define SDCR_RESET_VAL 0x0
dp-arm595d0d52017-02-08 11:51:50 +0000113
David Cunadofee86532017-04-13 22:38:29 +0100114#if !ERROR_DEPRECATED
dp-arm595d0d52017-02-08 11:51:50 +0000115#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
David Cunadofee86532017-04-13 22:38:29 +0100116#endif
dp-arm595d0d52017-02-08 11:51:50 +0000117
Soby Mathewc6820d12016-05-09 17:49:55 +0100118/* HSCTLR definitions */
119#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \
120 | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \
Soby Mathewa993c422016-09-29 14:15:57 +0100121 | (1 << 3))
Soby Mathewc6820d12016-05-09 17:49:55 +0100122#define HSCTLR_M_BIT (1 << 0)
123#define HSCTLR_A_BIT (1 << 1)
124#define HSCTLR_C_BIT (1 << 2)
125#define HSCTLR_CP15BEN_BIT (1 << 5)
126#define HSCTLR_ITD_BIT (1 << 7)
127#define HSCTLR_SED_BIT (1 << 8)
128#define HSCTLR_I_BIT (1 << 12)
129#define HSCTLR_WXN_BIT (1 << 19)
130#define HSCTLR_EE_BIT (1 << 25)
131#define HSCTLR_TE_BIT (1 << 30)
132
133/* CPACR definitions */
134#define CPACR_FPEN(x) ((x) << 20)
135#define CPACR_FP_TRAP_PL0 0x1
136#define CPACR_FP_TRAP_ALL 0x2
137#define CPACR_FP_TRAP_NONE 0x3
138
139/* SCR definitions */
140#define SCR_TWE_BIT (1 << 13)
141#define SCR_TWI_BIT (1 << 12)
142#define SCR_SIF_BIT (1 << 9)
143#define SCR_HCE_BIT (1 << 8)
144#define SCR_SCD_BIT (1 << 7)
145#define SCR_NET_BIT (1 << 6)
146#define SCR_AW_BIT (1 << 5)
147#define SCR_FW_BIT (1 << 4)
148#define SCR_EA_BIT (1 << 3)
149#define SCR_FIQ_BIT (1 << 2)
150#define SCR_IRQ_BIT (1 << 1)
151#define SCR_NS_BIT (1 << 0)
152#define SCR_VALID_BIT_MASK 0x33ff
David Cunadofee86532017-04-13 22:38:29 +0100153#define SCR_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100154
155#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
156
157/* HCR definitions */
158#define HCR_AMO_BIT (1 << 5)
159#define HCR_IMO_BIT (1 << 4)
160#define HCR_FMO_BIT (1 << 3)
David Cunadofee86532017-04-13 22:38:29 +0100161#define HCR_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100162
163/* CNTHCTL definitions */
David Cunadofee86532017-04-13 22:38:29 +0100164#define CNTHCTL_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100165#define PL1PCEN_BIT (1 << 1)
166#define PL1PCTEN_BIT (1 << 0)
167
168/* CNTKCTL definitions */
169#define PL0PTEN_BIT (1 << 9)
170#define PL0VTEN_BIT (1 << 8)
171#define PL0PCTEN_BIT (1 << 0)
172#define PL0VCTEN_BIT (1 << 1)
173#define EVNTEN_BIT (1 << 2)
174#define EVNTDIR_BIT (1 << 3)
175#define EVNTI_SHIFT 4
176#define EVNTI_MASK 0xf
177
178/* HCPTR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100179#define HCPTR_RES1 ((1 << 13) | (1<<12) | 0x3ff)
Soby Mathewc6820d12016-05-09 17:49:55 +0100180#define TCPAC_BIT (1 << 31)
181#define TTA_BIT (1 << 20)
182#define TCP11_BIT (1 << 10)
183#define TCP10_BIT (1 << 10)
David Cunadofee86532017-04-13 22:38:29 +0100184#define HCPTR_RESET_VAL HCPTR_RES1
185
186/* VTTBR defintions */
187#define VTTBR_RESET_VAL ULL(0x0)
188#define VTTBR_VMID_MASK ULL(0xff)
189#define VTTBR_VMID_SHIFT 48
190#define VTTBR_BADDR_MASK 0xffffffffffff
191#define VTTBR_BADDR_SHIFT 0
192
193/* HDCR definitions */
194#define HDCR_RESET_VAL 0x0
195
196/* HSTR definitions */
197#define HSTR_RESET_VAL 0x0
198
199/* CNTHP_CTL definitions */
200#define CNTHP_CTL_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100201
202/* NASCR definitions */
203#define NSASEDIS_BIT (1 << 15)
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100204#define NSTRCDIS_BIT (1 << 20)
David Cunadofee86532017-04-13 22:38:29 +0100205/* NOTE: correct typo in the definitions */
206#if !ERROR_DEPRECATED
Soby Mathewc6820d12016-05-09 17:49:55 +0100207#define NASCR_CP11_BIT (1 << 11)
208#define NASCR_CP10_BIT (1 << 10)
David Cunadofee86532017-04-13 22:38:29 +0100209#endif
210#define NSACR_CP11_BIT (1 << 11)
211#define NSACR_CP10_BIT (1 << 10)
212#define NSACR_IMP_DEF_MASK (0x7 << 16)
213#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
214#define NSACR_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100215
216/* CPACR definitions */
217#define ASEDIS_BIT (1 << 31)
218#define TRCDIS_BIT (1 << 28)
219#define CPACR_CP11_SHIFT 22
220#define CPACR_CP10_SHIFT 20
221#define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\
222 0x3 << CPACR_CP10_SHIFT)
David Cunadofee86532017-04-13 22:38:29 +0100223#define CPACR_RESET_VAL 0x0
Soby Mathewc6820d12016-05-09 17:49:55 +0100224
225/* FPEXC definitions */
David Cunadofee86532017-04-13 22:38:29 +0100226#define FPEXC_RES1 ((1 << 10) | (1 << 9) | (1 << 8))
Soby Mathewc6820d12016-05-09 17:49:55 +0100227#define FPEXC_EN_BIT (1 << 30)
David Cunadofee86532017-04-13 22:38:29 +0100228#define FPEXC_RESET_VAL FPEXC_RES1
Soby Mathewc6820d12016-05-09 17:49:55 +0100229
230/* SPSR/CPSR definitions */
231#define SPSR_FIQ_BIT (1 << 0)
232#define SPSR_IRQ_BIT (1 << 1)
233#define SPSR_ABT_BIT (1 << 2)
234#define SPSR_AIF_SHIFT 6
235#define SPSR_AIF_MASK 0x7
236
237#define SPSR_E_SHIFT 9
238#define SPSR_E_MASK 0x1
239#define SPSR_E_LITTLE 0
240#define SPSR_E_BIG 1
241
242#define SPSR_T_SHIFT 5
243#define SPSR_T_MASK 0x1
244#define SPSR_T_ARM 0
245#define SPSR_T_THUMB 1
246
247#define SPSR_MODE_SHIFT 0
248#define SPSR_MODE_MASK 0x7
249
250
251#define DISABLE_ALL_EXCEPTIONS \
252 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
253
254/*
255 * TTBCR definitions
256 */
257/* The ARM Trusted Firmware uses the long descriptor format */
258#define TTBCR_EAE_BIT (1 << 31)
259
260#define TTBCR_SH1_NON_SHAREABLE (0x0 << 28)
261#define TTBCR_SH1_OUTER_SHAREABLE (0x2 << 28)
262#define TTBCR_SH1_INNER_SHAREABLE (0x3 << 28)
263
264#define TTBCR_RGN1_OUTER_NC (0x0 << 26)
265#define TTBCR_RGN1_OUTER_WBA (0x1 << 26)
266#define TTBCR_RGN1_OUTER_WT (0x2 << 26)
267#define TTBCR_RGN1_OUTER_WBNA (0x3 << 26)
268
269#define TTBCR_RGN1_INNER_NC (0x0 << 24)
270#define TTBCR_RGN1_INNER_WBA (0x1 << 24)
271#define TTBCR_RGN1_INNER_WT (0x2 << 24)
272#define TTBCR_RGN1_INNER_WBNA (0x3 << 24)
273
274#define TTBCR_EPD1_BIT (1 << 23)
275#define TTBCR_A1_BIT (1 << 22)
276
277#define TTBCR_T1SZ_SHIFT 16
278#define TTBCR_T1SZ_MASK (0x7)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100279#define TTBCR_TxSZ_MIN 0
280#define TTBCR_TxSZ_MAX 7
Soby Mathewc6820d12016-05-09 17:49:55 +0100281
282#define TTBCR_SH0_NON_SHAREABLE (0x0 << 12)
283#define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12)
284#define TTBCR_SH0_INNER_SHAREABLE (0x3 << 12)
285
286#define TTBCR_RGN0_OUTER_NC (0x0 << 10)
287#define TTBCR_RGN0_OUTER_WBA (0x1 << 10)
288#define TTBCR_RGN0_OUTER_WT (0x2 << 10)
289#define TTBCR_RGN0_OUTER_WBNA (0x3 << 10)
290
291#define TTBCR_RGN0_INNER_NC (0x0 << 8)
292#define TTBCR_RGN0_INNER_WBA (0x1 << 8)
293#define TTBCR_RGN0_INNER_WT (0x2 << 8)
294#define TTBCR_RGN0_INNER_WBNA (0x3 << 8)
295
296#define TTBCR_EPD0_BIT (1 << 7)
297#define TTBCR_T0SZ_SHIFT 0
298#define TTBCR_T0SZ_MASK (0x7)
299
300#define MODE_RW_SHIFT 0x4
301#define MODE_RW_MASK 0x1
302#define MODE_RW_32 0x1
303
304#define MODE32_SHIFT 0
305#define MODE32_MASK 0x1f
306#define MODE32_usr 0x10
307#define MODE32_fiq 0x11
308#define MODE32_irq 0x12
309#define MODE32_svc 0x13
310#define MODE32_mon 0x16
311#define MODE32_abt 0x17
312#define MODE32_hyp 0x1a
313#define MODE32_und 0x1b
314#define MODE32_sys 0x1f
315
316#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
317
318#define SPSR_MODE32(mode, isa, endian, aif) \
319 (MODE_RW_32 << MODE_RW_SHIFT | \
320 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
321 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
322 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
323 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
324
325/*
326 * CTR definitions
327 */
328#define CTR_CWG_SHIFT 24
329#define CTR_CWG_MASK 0xf
330#define CTR_ERG_SHIFT 20
331#define CTR_ERG_MASK 0xf
332#define CTR_DMINLINE_SHIFT 16
333#define CTR_DMINLINE_WIDTH 4
334#define CTR_DMINLINE_MASK ((1 << 4) - 1)
335#define CTR_L1IP_SHIFT 14
336#define CTR_L1IP_MASK 0x3
337#define CTR_IMINLINE_SHIFT 0
338#define CTR_IMINLINE_MASK 0xf
339
340#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
341
David Cunado5f55e282016-10-31 17:37:34 +0000342/* PMCR definitions */
343#define PMCR_N_SHIFT 11
344#define PMCR_N_MASK 0x1f
345#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
346
Soby Mathewc6820d12016-05-09 17:49:55 +0100347/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000348 * Definitions of register offsets, fields and macros for CPU system
349 * instructions.
350 ******************************************************************************/
351
352#define TLBI_ADDR_SHIFT 0
353#define TLBI_ADDR_MASK 0xFFFFF000
354#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
355
356/*******************************************************************************
Soby Mathewc6820d12016-05-09 17:49:55 +0100357 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
358 * system level implementation of the Generic Timer.
359 ******************************************************************************/
360#define CNTNSAR 0x4
361#define CNTNSAR_NS_SHIFT(x) (x)
362
363#define CNTACR_BASE(x) (0x40 + ((x) << 2))
364#define CNTACR_RPCT_SHIFT 0x0
365#define CNTACR_RVCT_SHIFT 0x1
366#define CNTACR_RFRQ_SHIFT 0x2
367#define CNTACR_RVOFF_SHIFT 0x3
368#define CNTACR_RWVT_SHIFT 0x4
369#define CNTACR_RWPT_SHIFT 0x5
370
371/* MAIR macros */
372#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
373#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3))
374
375/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
376#define SCR p15, 0, c1, c1, 0
377#define SCTLR p15, 0, c1, c0, 0
dp-arm595d0d52017-02-08 11:51:50 +0000378#define SDCR p15, 0, c1, c3, 1
Soby Mathewc6820d12016-05-09 17:49:55 +0100379#define MPIDR p15, 0, c0, c0, 5
380#define MIDR p15, 0, c0, c0, 0
381#define VBAR p15, 0, c12, c0, 0
382#define MVBAR p15, 0, c12, c0, 1
383#define NSACR p15, 0, c1, c1, 2
384#define CPACR p15, 0, c1, c0, 2
385#define DCCIMVAC p15, 0, c7, c14, 1
386#define DCCMVAC p15, 0, c7, c10, 1
387#define DCIMVAC p15, 0, c7, c6, 1
388#define DCCISW p15, 0, c7, c14, 2
389#define DCCSW p15, 0, c7, c10, 2
390#define DCISW p15, 0, c7, c6, 2
391#define CTR p15, 0, c0, c0, 1
392#define CNTFRQ p15, 0, c14, c0, 0
393#define ID_PFR1 p15, 0, c0, c1, 1
394#define MAIR0 p15, 0, c10, c2, 0
395#define MAIR1 p15, 0, c10, c2, 1
396#define TTBCR p15, 0, c2, c0, 2
397#define TTBR0 p15, 0, c2, c0, 0
398#define TTBR1 p15, 0, c2, c0, 1
399#define TLBIALL p15, 0, c8, c7, 0
400#define TLBIALLIS p15, 0, c8, c3, 0
401#define TLBIMVA p15, 0, c8, c7, 1
402#define TLBIMVAA p15, 0, c8, c7, 3
Antonio Nino Diazac998032017-02-27 17:23:54 +0000403#define TLBIMVAAIS p15, 0, c8, c3, 3
404#define BPIALLIS p15, 0, c7, c1, 6
Soby Mathewc6820d12016-05-09 17:49:55 +0100405#define HSCTLR p15, 4, c1, c0, 0
406#define HCR p15, 4, c1, c1, 0
407#define HCPTR p15, 4, c1, c1, 2
David Cunadofee86532017-04-13 22:38:29 +0100408#define HSTR p15, 4, c1, c1, 3
Soby Mathewc6820d12016-05-09 17:49:55 +0100409#define CNTHCTL p15, 4, c14, c1, 0
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000410#define CNTKCTL p15, 0, c14, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100411#define VPIDR p15, 4, c0, c0, 0
412#define VMPIDR p15, 4, c0, c0, 5
413#define ISR p15, 0, c12, c1, 0
414#define CLIDR p15, 1, c0, c0, 1
415#define CSSELR p15, 2, c0, c0, 0
416#define CCSIDR p15, 1, c0, c0, 0
Yatharth Kochara9f776c2016-11-10 16:17:51 +0000417#define DBGOSDLR p14, 0, c1, c3, 4
Soby Mathewc6820d12016-05-09 17:49:55 +0100418
David Cunado5f55e282016-10-31 17:37:34 +0000419/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
420#define HDCR p15, 4, c1, c1, 1
David Cunado5f55e282016-10-31 17:37:34 +0000421#define PMCR p15, 0, c9, c12, 0
David Cunadoc14b08e2016-11-25 00:21:59 +0000422#define CNTHP_CTL p15, 4, c14, c2, 1
David Cunado5f55e282016-10-31 17:37:34 +0000423
Soby Mathewc6820d12016-05-09 17:49:55 +0100424/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
425#define ICC_IAR1 p15, 0, c12, c12, 0
426#define ICC_IAR0 p15, 0, c12, c8, 0
427#define ICC_EOIR1 p15, 0, c12, c12, 1
428#define ICC_EOIR0 p15, 0, c12, c8, 1
429#define ICC_HPPIR1 p15, 0, c12, c12, 2
430#define ICC_HPPIR0 p15, 0, c12, c8, 2
431#define ICC_BPR1 p15, 0, c12, c12, 3
432#define ICC_BPR0 p15, 0, c12, c8, 3
433#define ICC_DIR p15, 0, c12, c11, 1
434#define ICC_PMR p15, 0, c4, c6, 0
435#define ICC_RPR p15, 0, c12, c11, 3
436#define ICC_CTLR p15, 0, c12, c12, 4
437#define ICC_MCTLR p15, 6, c12, c12, 4
438#define ICC_SRE p15, 0, c12, c12, 5
439#define ICC_HSRE p15, 4, c12, c9, 5
440#define ICC_MSRE p15, 6, c12, c12, 5
441#define ICC_IGRPEN0 p15, 0, c12, c12, 6
442#define ICC_IGRPEN1 p15, 0, c12, c12, 7
443#define ICC_MGRPEN1 p15, 6, c12, c12, 7
444
445/* 64 bit system register defines The format is: coproc, opt1, CRm */
446#define TTBR0_64 p15, 0, c2
447#define TTBR1_64 p15, 1, c2
448#define CNTVOFF_64 p15, 4, c14
449#define VTTBR_64 p15, 6, c2
450#define CNTPCT_64 p15, 0, c14
451
452/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
453#define ICC_SGI1R_EL1_64 p15, 0, c12
454#define ICC_ASGI1R_EL1_64 p15, 1, c12
455#define ICC_SGI0R_EL1_64 p15, 2, c12
456
457#endif /* __ARCH_H__ */