blob: 7fb64f3e4e68728e92c9c66aad1615e5862b216e [file] [log] [blame]
Yatharth Kochar18dfb302016-11-22 11:06:03 +00001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <bl_common.h>
10
11
12 .globl bl2u_vector_table
13 .globl bl2u_entrypoint
14
15
16vector_base bl2u_vector_table
17 b bl2u_entrypoint
18 b report_exception /* Undef */
19 b report_exception /* SVC call */
20 b report_exception /* Prefetch abort */
21 b report_exception /* Data abort */
22 b report_exception /* Reserved */
23 b report_exception /* IRQ */
24 b report_exception /* FIQ */
25
26
27func bl2u_entrypoint
28 /*---------------------------------------------
29 * Save from r1 the extents of the trusted ram
30 * available to BL2U for future use.
31 * r0 is not currently used.
32 * ---------------------------------------------
33 */
34 mov r11, r1
Douglas Raillard983b4752017-07-26 19:23:16 +010035 mov r10, r2
Yatharth Kochar18dfb302016-11-22 11:06:03 +000036
37 /* ---------------------------------------------
38 * Set the exception vector to something sane.
39 * ---------------------------------------------
40 */
41 ldr r0, =bl2u_vector_table
42 stcopr r0, VBAR
43 isb
44
45 /* -----------------------------------------------------
46 * Enable the instruction cache
47 * -----------------------------------------------------
48 */
49 ldcopr r0, SCTLR
50 orr r0, r0, #SCTLR_I_BIT
51 stcopr r0, SCTLR
52 isb
53
54 /* ---------------------------------------------
55 * Since BL2U executes after BL1, it is assumed
56 * here that BL1 has already has done the
57 * necessary register initializations.
58 * ---------------------------------------------
59 */
60
61 /* ---------------------------------------------
62 * Invalidate the RW memory used by the BL2U
63 * image. This includes the data and NOBITS
64 * sections. This is done to safeguard against
65 * possible corruption of this memory by dirty
66 * cache lines in a system cache as a result of
67 * use by an earlier boot loader stage.
68 * ---------------------------------------------
69 */
70 ldr r0, =__RW_START__
71 ldr r1, =__RW_END__
72 sub r1, r1, r0
73 bl inv_dcache_range
74
75 /* ---------------------------------------------
76 * Zero out NOBITS sections. There are 2 of them:
77 * - the .bss section;
78 * - the coherent memory section.
79 * ---------------------------------------------
80 */
81 ldr r0, =__BSS_START__
82 ldr r1, =__BSS_SIZE__
83 bl zeromem
84
85 /* --------------------------------------------
86 * Allocate a stack whose memory will be marked
87 * as Normal-IS-WBWA when the MMU is enabled.
88 * There is no risk of reading stale stack
89 * memory after enabling the MMU as only the
90 * primary cpu is running at the moment.
91 * --------------------------------------------
92 */
93 bl plat_set_my_stack
94
95 /* ---------------------------------------------
96 * Initialize the stack protector canary before
97 * any C code is called.
98 * ---------------------------------------------
99 */
100#if STACK_PROTECTOR_ENABLED
101 bl update_stack_protector_canary
102#endif
103
104 /* ---------------------------------------------
105 * Perform early platform setup & platform
106 * specific early arch. setup e.g. mmu setup
107 * ---------------------------------------------
108 */
109 mov r0, r11
Douglas Raillard983b4752017-07-26 19:23:16 +0100110 mov r1, r10
Yatharth Kochar18dfb302016-11-22 11:06:03 +0000111 bl bl2u_early_platform_setup
112 bl bl2u_plat_arch_setup
113
114 /* ---------------------------------------------
115 * Jump to main function.
116 * ---------------------------------------------
117 */
118 bl bl2u_main
119
120 /* ---------------------------------------------
121 * Should never reach this point.
122 * ---------------------------------------------
123 */
124 no_ret plat_panic_handler
125
126endfunc bl2u_entrypoint