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Joel Huttona7c46872018-01-10 16:06:07 +00001/*
John Tsichritzis16e6d9f2019-02-19 14:01:55 +00002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Joel Huttona7c46872018-01-10 16:06:07 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <arch.h>
7#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/bl_common.h>
9#include <common/debug.h>
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000010#include <neoverse_e1.h>
Joel Huttona7c46872018-01-10 16:06:07 +000011#include <cpu_macros.S>
Joel Huttona7c46872018-01-10 16:06:07 +000012#include <plat_macros.S>
13
John Tsichritzisfe6df392019-03-19 17:20:52 +000014/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
John Tsichritzis7557c662019-06-03 13:54:30 +010019/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
Louis Mayencourt8b8b13b2019-06-10 16:43:39 +010024 /* -------------------------------------------------
25 * The CPU Ops reset function for Neoverse-E1.
26 * Shall clobber: x0-x19
27 * -------------------------------------------------
28 */
29func neoverse_e1_reset_func
30 mov x19, x30
31
32#if ERRATA_DSU_936184
33 bl errata_dsu_936184_wa
34#endif
35
36 ret x19
37endfunc neoverse_e1_reset_func
38
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000039func neoverse_e1_cpu_pwr_dwn
40 mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
41 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
42 msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0
Joel Huttona7c46872018-01-10 16:06:07 +000043 isb
44 ret
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000045endfunc neoverse_e1_cpu_pwr_dwn
Joel Huttona7c46872018-01-10 16:06:07 +000046
Soby Mathew0980dce2018-09-17 04:34:35 +010047#if REPORT_ERRATA
48/*
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000049 * Errata printing function for Neoverse N1. Must follow AAPCS.
Soby Mathew0980dce2018-09-17 04:34:35 +010050 */
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000051func neoverse_e1_errata_report
Louis Mayencourt8b8b13b2019-06-10 16:43:39 +010052 stp x8, x30, [sp, #-16]!
53
54 bl cpu_get_rev_var
55 mov x8, x0
56
57 /*
58 * Report all errata. The revision-variant information is passed to
59 * checking functions of each errata.
60 */
61 report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184
62
63 ldp x8, x30, [sp], #16
Soby Mathew0980dce2018-09-17 04:34:35 +010064 ret
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000065endfunc neoverse_e1_errata_report
Soby Mathew0980dce2018-09-17 04:34:35 +010066#endif
67
68
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000069.section .rodata.neoverse_e1_regs, "aS"
70neoverse_e1_regs: /* The ascii list of register names to be reported */
Joel Huttona7c46872018-01-10 16:06:07 +000071 .asciz "cpuectlr_el1", ""
72
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000073func neoverse_e1_cpu_reg_dump
74 adr x6, neoverse_e1_regs
75 mrs x8, NEOVERSE_E1_ECTLR_EL1
Joel Huttona7c46872018-01-10 16:06:07 +000076 ret
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000077endfunc neoverse_e1_cpu_reg_dump
Joel Huttona7c46872018-01-10 16:06:07 +000078
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000079declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \
Louis Mayencourt8b8b13b2019-06-10 16:43:39 +010080 neoverse_e1_reset_func, \
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000081 neoverse_e1_cpu_pwr_dwn