blob: e82f3a32ed19decc0feae56e920ab0d118f8c034 [file] [log] [blame]
Achin Gupta07f4e072014-02-02 12:02:23 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
Dan Handley2bd4ef22014-04-09 13:14:54 +010030#include <arch.h>
31#include <context.h>
32
Achin Gupta07f4e072014-02-02 12:02:23 +000033 .macro switch_to_exception_stack reg1 reg2
34 mov \reg1 , sp
35 ldr \reg2, [\reg1, #CTX_EL3STATE_OFFSET + CTX_EXCEPTION_SP]
36 mov sp, \reg2
37 .endm
38
39 /* -----------------------------------------------------
40 * Handle SMC exceptions seperately from other sync.
41 * exceptions.
42 * -----------------------------------------------------
43 */
44 .macro handle_sync_exception
Soby Mathew6c5192a2014-04-30 15:36:37 +010045 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Achin Gupta07f4e072014-02-02 12:02:23 +000046 mrs x30, esr_el3
47 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
48
49 cmp x30, #EC_AARCH32_SMC
50 b.eq smc_handler32
51
52 cmp x30, #EC_AARCH64_SMC
53 b.eq smc_handler64
54
55 /* -----------------------------------------------------
56 * The following code handles any synchronous exception
57 * that is not an SMC. SP_EL3 is pointing to a context
58 * structure where all the scratch registers are saved.
59 * An exception stack is also retrieved from the context
60 * Currently, a register dump is printed since BL31 does
61 * not expect any such exceptions.
62 * -----------------------------------------------------
63 */
Soby Mathew6c5192a2014-04-30 15:36:37 +010064 bl save_gp_registers
Achin Gupta07f4e072014-02-02 12:02:23 +000065 switch_to_exception_stack x0 x1
66
67 /* Save the core_context pointer for handled faults */
68 stp x0, xzr, [sp, #-0x10]!
69 bl fault_handler
70 ldp x0, xzr, [sp], #0x10
71
72 mov sp, x0
Soby Mathew6c5192a2014-04-30 15:36:37 +010073 bl restore_gp_registers
74 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Achin Gupta07f4e072014-02-02 12:02:23 +000075 eret
76 .endm
77
78 /* -----------------------------------------------------
79 * Use a platform defined mechanism to report an async.
80 * exception.
81 * -----------------------------------------------------
82 */
83 .macro handle_async_exception type
Soby Mathew6c5192a2014-04-30 15:36:37 +010084 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
85 bl save_gp_registers
Achin Gupta07f4e072014-02-02 12:02:23 +000086 switch_to_exception_stack x0 x1
87
88 /* Save the core_context pointer */
89 stp x0, xzr, [sp, #-0x10]!
90 mov x0, \type
91 bl plat_report_exception
92 ldp x0, xzr, [sp], #0x10
93
94 mov sp, x0
Soby Mathew6c5192a2014-04-30 15:36:37 +010095 bl restore_gp_registers
96 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Achin Gupta07f4e072014-02-02 12:02:23 +000097 .endm
98