| Haojian Zhuang | 5f281b3 | 2017-05-24 08:45:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __HIKEY_DEF_H__ |
| 8 | #define __HIKEY_DEF_H__ |
| 9 | |
| 10 | #include <common_def.h> |
| 11 | #include <tbbr_img_def.h> |
| 12 | |
| 13 | /* Always assume DDR is 1GB size. */ |
| 14 | #define DDR_BASE 0x0 |
| 15 | #define DDR_SIZE 0x80000000 |
| 16 | |
| 17 | #define DEVICE_BASE 0xF4000000 |
| 18 | #define DEVICE_SIZE 0x05800000 |
| 19 | |
| 20 | #define XG2RAM0_BASE 0xF9800000 |
| 21 | #define XG2RAM0_SIZE 0x00400000 |
| 22 | |
| 23 | #define SRAM_BASE 0xFFF80000 |
| 24 | #define SRAM_SIZE 0x00012000 |
| 25 | |
| 26 | /* |
| 27 | * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). |
| 28 | */ |
| 29 | #define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) |
| 30 | #define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) |
| 31 | #define BL1_XG2RAM0_OFFSET 0x1000 |
| 32 | |
| 33 | /* |
| 34 | * PL011 related constants |
| 35 | */ |
| 36 | #define PL011_UART0_BASE 0xF8015000 |
| 37 | #define PL011_UART3_BASE 0xF7113000 |
| 38 | #define PL011_BAUDRATE 115200 |
| 39 | #define PL011_UART_CLK_IN_HZ 19200000 |
| 40 | |
| 41 | #define HIKEY_USB_DESC_BASE (DDR_BASE + 0x00800000) |
| 42 | #define HIKEY_USB_DESC_SIZE 0x00100000 |
| 43 | #define HIKEY_USB_DATA_BASE (DDR_BASE + 0x10000000) |
| 44 | #define HIKEY_USB_DATA_SIZE 0x10000000 |
| 45 | #define HIKEY_FB_BUFFER_BASE (HIKEY_USB_DATA_BASE) |
| 46 | #define HIKEY_FB_BUFFER_SIZE HIKEY_USB_DATA_SIZE |
| 47 | #define HIKEY_FB_DOWNLOAD_BASE (HIKEY_FB_BUFFER_BASE + \ |
| 48 | HIKEY_FB_BUFFER_SIZE) |
| 49 | #define HIKEY_FB_DOWNLOAD_SIZE HIKEY_USB_DATA_SIZE |
| 50 | |
| 51 | #define HIKEY_USB_DESC_IN_BASE (DDR_BASE + 0x00800000) |
| 52 | #define HIKEY_USB_DESC_IN_SIZE 0x00040000 |
| 53 | #define HIKEY_USB_DESC_EP0_OUT_BASE (HIKEY_USB_DESC_IN_BASE + \ |
| 54 | HIKEY_USB_DESC_IN_SIZE) |
| 55 | #define HIKEY_USB_DESC_EP0_OUT_SIZE 0x00040000 |
| 56 | #define HIKEY_USB_DESC_EPX_OUT_BASE (HIKEY_USB_DESC_EP0_OUT_BASE + \ |
| 57 | HIKEY_USB_DESC_EP0_OUT_SIZE) |
| 58 | #define HIKEY_USB_DESC_EPX_OUT_SIZE 0x00080000 |
| 59 | |
| 60 | #define HIKEY_MMC_DESC_BASE (DDR_BASE + 0x03000000) |
| 61 | #define HIKEY_MMC_DESC_SIZE 0x00100000 |
| 62 | |
| 63 | /* |
| 64 | * HIKEY_MMC_DATA_BASE & HIKEY_MMC_DATA_SIZE are shared between fastboot |
| 65 | * and eMMC driver. Since it could avoid to memory copy. |
| 66 | * So this SRAM region is used twice. First, it's used in BL1 as temporary |
| 67 | * buffer in eMMC driver. Second, it's used by MCU in BL2. The SRAM region |
| 68 | * needs to be clear before used in BL2. |
| 69 | */ |
| 70 | #define HIKEY_MMC_DATA_BASE (DDR_BASE + 0x10000000) |
| 71 | #define HIKEY_MMC_DATA_SIZE 0x20000000 |
| 72 | #define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000) |
| 73 | #define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE) |
| 74 | #define HIKEY_BL1_MMC_DESC_SIZE 0x00001000 |
| 75 | #define HIKEY_BL1_MMC_DATA_BASE (HIKEY_BL1_MMC_DESC_BASE + \ |
| 76 | HIKEY_BL1_MMC_DESC_SIZE) |
| 77 | #define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000 |
| 78 | |
| 79 | #define EMMC_BASE 0 |
| 80 | #define HIKEY_FIP_BASE (EMMC_BASE + (4 << 20)) |
| 81 | #define HIKEY_FIP_MAX_SIZE (8 << 20) |
| 82 | #define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0) |
| 83 | #define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10) |
| 84 | #define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0) |
| 85 | #define HIKEY_EMMC_USERDATA_MAX_SIZE (4 << 30) |
| 86 | |
| 87 | /* |
| 88 | * GIC400 interrupt handling related constants |
| 89 | */ |
| 90 | #define IRQ_SEC_PHY_TIMER 29 |
| 91 | #define IRQ_SEC_SGI_0 8 |
| 92 | #define IRQ_SEC_SGI_1 9 |
| 93 | #define IRQ_SEC_SGI_2 10 |
| 94 | #define IRQ_SEC_SGI_3 11 |
| 95 | #define IRQ_SEC_SGI_4 12 |
| 96 | #define IRQ_SEC_SGI_5 13 |
| 97 | #define IRQ_SEC_SGI_6 14 |
| 98 | #define IRQ_SEC_SGI_7 15 |
| 99 | #define IRQ_SEC_SGI_8 16 |
| 100 | |
| 101 | #endif /* __HIKEY_DEF_H__ */ |