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git01.mediatek.com / filogic / atf / 961931ce883196544ea051bfc462b77f2c738938 / . / plat / renesas / rcar / bl2_secure_setting.c
blob: 7473df5a21a5ca46e420c544dac2d273b2e1f401 [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]7#include <lib/mmio.h>
8#include <lib/utils_def.h>
9
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]10#include "axi_registers.h"
11#include "lifec_registers.h"
12#include "micro_delay.h"
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]13
14static void lifec_security_setting(void);
15static void axi_security_setting(void);
16
17static const struct {
18 uint32_t reg;
19 uint32_t val;
20} lifec[] = {
21 /** LIFEC0 (SECURITY) settings */
22 /* Security attribute setting for master ports */
23 /* Bit 0: ARM realtime core (Cortex-R7) master port */
24 /* 0: Non-Secure */
25 {
26 SEC_SRC, 0x0000001EU},
27 /** Security attribute setting for slave ports 0 to 15 */
28 /* {SEC_SEL0, 0xFFFFFFFFU}, */
29 /* {SEC_SEL1, 0xFFFFFFFFU}, */
30 /* {SEC_SEL2, 0xFFFFFFFFU}, */
31 /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports */
32 /* 0: registers accessed from secure resource only */
33 /* Bit 9: DBSC4 register access slave ports. */
34 /* 0: registers accessed from secure resource only. */
35#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
36 {
37 SEC_SEL3, 0xFFF7FDFFU},
38#else
39 {
40 SEC_SEL3, 0xFFFFFFFFU},
41#endif
42 /* {SEC_SEL4, 0xFFFFFFFFU}, */
43 /* Bit 6: Boot ROM slave ports. */
44 /* 0: registers accessed from secure resource only */
45 {
46 SEC_SEL5, 0xFFFFFFBFU},
47 /* Bit13: SCEG PKA (secure APB) slave ports */
48 /* 0: registers accessed from secure resource only */
49 /* 1: Reserved[R-Car E3] */
50 /* Bit12: SCEG PKA (public APB) slave ports */
51 /* 0: registers accessed from secure resource only */
52 /* 1: Reserved[R-Car E3] */
53 /* Bit10: SCEG Secure Core slave ports */
54 /* 0: registers accessed from secure resource only */
Marek Vasut4ae342c2019-01-05 13:56:03 +0100[diff] [blame]55#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]56 {
57 SEC_SEL6, 0xFFFFFBFFU},
58#else
59 {
60 SEC_SEL6, 0xFFFFCBFFU},
61#endif
62 /* {SEC_SEL7, 0xFFFFFFFFU}, */
63 /* {SEC_SEL8, 0xFFFFFFFFU}, */
64 /* {SEC_SEL9, 0xFFFFFFFFU}, */
65 /* {SEC_SEL10, 0xFFFFFFFFU}, */
66 /* {SEC_SEL11, 0xFFFFFFFFU}, */
67 /* {SEC_SEL12, 0xFFFFFFFFU}, */
68 /* Bit22: RPC slave ports. */
69 /* 0: registers accessed from secure resource only. */
Jorge Ramirez-Ortiz87c04052018-11-19 19:26:56 +0100[diff] [blame]70#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
71 {SEC_SEL13, 0xFFBFFFFFU},
72#endif
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]73 /* Bit27: System Timer (SCMT) slave ports */
74 /* 0: registers accessed from secure resource only */
75 /* Bit26: System Watchdog Timer (SWDT) slave ports */
76 /* 0: registers accessed from secure resource only */
77 {
78 SEC_SEL14, 0xF3FFFFFFU},
79 /* Bit13: RST slave ports. */
80 /* 0: registers accessed from secure resource only */
81 /* Bit 7: Life Cycle 0 slave ports */
82 /* 0: registers accessed from secure resource only */
83 {
84 SEC_SEL15, 0xFFFFFF3FU},
85 /** Security group 0 attribute setting for master ports 0 */
86 /** Security group 1 attribute setting for master ports 0 */
87 /* {SEC_GRP0CR0, 0x00000000U}, */
88 /* {SEC_GRP1CR0, 0x00000000U}, */
89 /** Security group 0 attribute setting for master ports 1 */
90 /** Security group 1 attribute setting for master ports 1 */
91 /* {SEC_GRP0CR1, 0x00000000U}, */
92 /* {SEC_GRP1CR1, 0x00000000U}, */
93 /** Security group 0 attribute setting for master ports 2 */
94 /** Security group 1 attribute setting for master ports 2 */
95 /* Bit17: SCEG Secure Core master ports. */
96 /* SecurityGroup3 */
97 {
98 SEC_GRP0CR2, 0x00020000U}, {
99 SEC_GRP1CR2, 0x00020000U},
100 /** Security group 0 attribute setting for master ports 3 */
101 /** Security group 1 attribute setting for master ports 3 */
102 /* {SEC_GRP0CR3, 0x00000000U}, */
103 /* {SEC_GRP1CR3, 0x00000000U}, */
104 /** Security group 0 attribute setting for slave ports 0 */
105 /** Security group 1 attribute setting for slave ports 0 */
106 /* {SEC_GRP0COND0, 0x00000000U}, */
107 /* {SEC_GRP1COND0, 0x00000000U}, */
108 /** Security group 0 attribute setting for slave ports 1 */
109 /** Security group 1 attribute setting for slave ports 1 */
110 /* {SEC_GRP0COND1, 0x00000000U}, */
111 /* {SEC_GRP1COND1, 0x00000000U}, */
112 /** Security group 0 attribute setting for slave ports 2 */
113 /** Security group 1 attribute setting for slave ports 2 */
114 /* {SEC_GRP0COND2, 0x00000000U}, */
115 /* {SEC_GRP1COND2, 0x00000000U}, */
116 /** Security group 0 attribute setting for slave ports 3 */
117 /** Security group 1 attribute setting for slave ports 3 */
118 /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports. */
119 /* SecurityGroup3 */
120 /* Bit 9: DBSC4 register access slave ports. */
121 /* SecurityGroup3 */
122#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
123 {
124 SEC_GRP0COND3, 0x00080200U}, {
125 SEC_GRP1COND3, 0x00080200U},
126#else
127 {
128 SEC_GRP0COND3, 0x00000000U}, {
129 SEC_GRP1COND3, 0x00000000U},
130#endif
131 /** Security group 0 attribute setting for slave ports 4 */
132 /** Security group 1 attribute setting for slave ports 4 */
133 /* {SEC_GRP0COND4, 0x00000000U}, */
134 /* {SEC_GRP1COND4, 0x00000000U}, */
135 /** Security group 0 attribute setting for slave ports 5 */
136 /** Security group 1 attribute setting for slave ports 5 */
137 /* Bit 6: Boot ROM slave ports */
138 /* SecurityGroup3 */
139 {
140 SEC_GRP0COND5, 0x00000040U}, {
141 SEC_GRP1COND5, 0x00000040U},
142 /** Security group 0 attribute setting for slave ports 6 */
143 /** Security group 1 attribute setting for slave ports 6 */
144 /* Bit13: SCEG PKA (secure APB) slave ports */
145 /* SecurityGroup3 */
146 /* Reserved[R-Car E3] */
147 /* Bit12: SCEG PKA (public APB) slave ports */
148 /* SecurityGroup3 */
149 /* Reserved[R-Car E3] */
150 /* Bit10: SCEG Secure Core slave ports */
151 /* SecurityGroup3 */
152#if RCAR_LSI == RCAR_E3
153 {
154 SEC_GRP0COND6, 0x00000400U}, {
155 SEC_GRP1COND6, 0x00000400U},
156#else
157 {
158 SEC_GRP0COND6, 0x00003400U}, {
159 SEC_GRP1COND6, 0x00003400U},
160#endif
161 /** Security group 0 attribute setting for slave ports 7 */
162 /** Security group 1 attribute setting for slave ports 7 */
163 /* {SEC_GRP0COND7, 0x00000000U}, */
164 /* {SEC_GRP1COND7, 0x00000000U}, */
165 /** Security group 0 attribute setting for slave ports 8 */
166 /** Security group 1 attribute setting for slave ports 8 */
167 /* {SEC_GRP0COND8, 0x00000000U}, */
168 /* {SEC_GRP1COND8, 0x00000000U}, */
169 /** Security group 0 attribute setting for slave ports 9 */
170 /** Security group 1 attribute setting for slave ports 9 */
171 /* {SEC_GRP0COND9, 0x00000000U}, */
172 /* {SEC_GRP1COND9, 0x00000000U}, */
173 /** Security group 0 attribute setting for slave ports 10 */
174 /** Security group 1 attribute setting for slave ports 10 */
175 /* {SEC_GRP0COND10, 0x00000000U}, */
176 /* {SEC_GRP1COND10, 0x00000000U}, */
177 /** Security group 0 attribute setting for slave ports 11 */
178 /** Security group 1 attribute setting for slave ports 11 */
179 /* {SEC_GRP0COND11, 0x00000000U}, */
180 /* {SEC_GRP1COND11, 0x00000000U}, */
181 /** Security group 0 attribute setting for slave ports 12 */
182 /** Security group 1 attribute setting for slave ports 12 */
183 /* {SEC_GRP0COND12, 0x00000000U}, */
184 /* {SEC_GRP1COND12, 0x00000000U}, */
185 /** Security group 0 attribute setting for slave ports 13 */
186 /** Security group 1 attribute setting for slave ports 13 */
187 /* Bit22: RPC slave ports. */
188 /* SecurityGroup3 */
Jorge Ramirez-Ortiz87c04052018-11-19 19:26:56 +0100[diff] [blame]189#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
190 {SEC_GRP0COND13, 0x00400000U},
191 {SEC_GRP1COND13, 0x00400000U},
192#endif
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]193 /** Security group 0 attribute setting for slave ports 14 */
194 /** Security group 1 attribute setting for slave ports 14 */
195 /* Bit26: System Timer (SCMT) slave ports */
196 /* SecurityGroup3 */
197 /* Bit27: System Watchdog Timer (SWDT) slave ports */
198 /* SecurityGroup3 */
199 {
200 SEC_GRP0COND14, 0x0C000000U}, {
201 SEC_GRP1COND14, 0x0C000000U},
202 /** Security group 0 attribute setting for slave ports 15 */
203 /** Security group 1 attribute setting for slave ports 15 */
204 /* Bit13: RST slave ports */
205 /* SecurityGroup3 */
206 /* Bit 7: Life Cycle 0 slave ports */
207 /* SecurityGroup3 */
208 /* Bit 6: TDBG slave ports */
209 /* SecurityGroup3 */
210 {
211 SEC_GRP0COND15, 0x000000C0U}, {
212 SEC_GRP1COND15, 0x000000C0U},
213 /** Security write protection attribute setting slave ports 0 */
214 /* {SEC_READONLY0, 0x00000000U}, */
215 /** Security write protection attribute setting slave ports 1 */
216 /* {SEC_READONLY1, 0x00000000U}, */
217 /** Security write protection attribute setting slave ports 2 */
218 /* {SEC_READONLY2, 0x00000000U}, */
219 /** Security write protection attribute setting slave ports 3 */
220 /* {SEC_READONLY3, 0x00000000U}, */
221 /** Security write protection attribute setting slave ports 4 */
222 /* {SEC_READONLY4, 0x00000000U}, */
223 /** Security write protection attribute setting slave ports 5 */
224 /* {SEC_READONLY5, 0x00000000U}, */
225 /** Security write protection attribute setting slave ports 6 */
226 /* {SEC_READONLY6, 0x00000000U}, */
227 /** Security write protection attribute setting slave ports 7 */
228 /* {SEC_READONLY7, 0x00000000U}, */
229 /** Security write protection attribute setting slave ports 8 */
230 /* {SEC_READONLY8, 0x00000000U}, */
231 /** Security write protection attribute setting slave ports 9 */
232 /* {SEC_READONLY9, 0x00000000U}, */
233 /** Security write protection attribute setting slave ports 10 */
234 /* {SEC_READONLY10, 0x00000000U}, */
235 /** Security write protection attribute setting slave ports 11 */
236 /* {SEC_READONLY11, 0x00000000U}, */
237 /** Security write protection attribute setting slave ports 12 */
238 /* {SEC_READONLY12, 0x00000000U}, */
239 /** Security write protection attribute setting slave ports 13 */
240 /* {SEC_READONLY13, 0x00000000U}, */
241 /** Security write protection attribute setting slave ports 14 */
242 /* {SEC_READONLY14, 0x00000000U}, */
243 /** Security write protection attribute setting slave ports 15 */
244 /* {SEC_READONLY15, 0x00000000U} */
245};
246
247/* AXI settings */
248static const struct {
249 uint32_t reg;
250 uint32_t val;
251} axi[] = {
252 /* DRAM protection */
253 /* AXI dram protected area division */
254 {
255 AXI_DPTDIVCR0, 0x0E0403F0U}, {
256 AXI_DPTDIVCR1, 0x0E0407E0U}, {
257 AXI_DPTDIVCR2, 0x0E080000U}, {
258 AXI_DPTDIVCR3, 0x0E080000U}, {
259 AXI_DPTDIVCR4, 0x0E080000U}, {
260 AXI_DPTDIVCR5, 0x0E080000U}, {
261 AXI_DPTDIVCR6, 0x0E080000U}, {
262 AXI_DPTDIVCR7, 0x0E080000U}, {
263 AXI_DPTDIVCR8, 0x0E080000U}, {
264 AXI_DPTDIVCR9, 0x0E080000U}, {
265 AXI_DPTDIVCR10, 0x0E080000U}, {
266 AXI_DPTDIVCR11, 0x0E080000U}, {
267 AXI_DPTDIVCR12, 0x0E080000U}, {
268 AXI_DPTDIVCR13, 0x0E080000U}, {
269 AXI_DPTDIVCR14, 0x0E080000U},
270 /* AXI dram protected area setting */
271 {
272 AXI_DPTCR0, 0x0E000000U}, {
273 AXI_DPTCR1, 0x0E000E0EU}, {
274 AXI_DPTCR2, 0x0E000000U}, {
275 AXI_DPTCR3, 0x0E000000U}, {
276 AXI_DPTCR4, 0x0E000000U}, {
277 AXI_DPTCR5, 0x0E000000U}, {
278 AXI_DPTCR6, 0x0E000000U}, {
279 AXI_DPTCR7, 0x0E000000U}, {
280 AXI_DPTCR8, 0x0E000000U}, {
281 AXI_DPTCR9, 0x0E000000U}, {
282 AXI_DPTCR10, 0x0E000000U}, {
283 AXI_DPTCR11, 0x0E000000U}, {
284 AXI_DPTCR12, 0x0E000000U}, {
285 AXI_DPTCR13, 0x0E000000U}, {
286 AXI_DPTCR14, 0x0E000000U}, {
287 AXI_DPTCR15, 0x0E000000U},
288 /* SRAM ptotection */
289 /* AXI sram protected area division */
290 {
291 AXI_SPTDIVCR0, 0x0E0E6304U}, {
292 AXI_SPTDIVCR1, 0x0E0E6360U}, {
293 AXI_SPTDIVCR2, 0x0E0E6360U}, {
294 AXI_SPTDIVCR3, 0x0E0E6360U}, {
295 AXI_SPTDIVCR4, 0x0E0E6360U}, {
296 AXI_SPTDIVCR5, 0x0E0E6360U}, {
297 AXI_SPTDIVCR6, 0x0E0E6360U}, {
298 AXI_SPTDIVCR7, 0x0E0E6360U}, {
299 AXI_SPTDIVCR8, 0x0E0E6360U}, {
300 AXI_SPTDIVCR9, 0x0E0E6360U}, {
301 AXI_SPTDIVCR10, 0x0E0E6360U}, {
302 AXI_SPTDIVCR11, 0x0E0E6360U}, {
303 AXI_SPTDIVCR12, 0x0E0E6360U}, {
304 AXI_SPTDIVCR13, 0x0E0E6360U}, {
305 AXI_SPTDIVCR14, 0x0E0E6360U},
306 /* AXI sram protected area setting */
307 {
308 AXI_SPTCR0, 0x0E000E0EU}, {
309 AXI_SPTCR1, 0x0E000000U}, {
310 AXI_SPTCR2, 0x0E000000U}, {
311 AXI_SPTCR3, 0x0E000000U}, {
312 AXI_SPTCR4, 0x0E000000U}, {
313 AXI_SPTCR5, 0x0E000000U}, {
314 AXI_SPTCR6, 0x0E000000U}, {
315 AXI_SPTCR7, 0x0E000000U}, {
316 AXI_SPTCR8, 0x0E000000U}, {
317 AXI_SPTCR9, 0x0E000000U}, {
318 AXI_SPTCR10, 0x0E000000U}, {
319 AXI_SPTCR11, 0x0E000000U}, {
320 AXI_SPTCR12, 0x0E000000U}, {
321 AXI_SPTCR13, 0x0E000000U}, {
322 AXI_SPTCR14, 0x0E000000U}, {
323 AXI_SPTCR15, 0x0E000000U}
324};
325
326static void lifec_security_setting(void)
327{
328 uint32_t i;
329
330 for (i = 0; i < ARRAY_SIZE(lifec); i++)
331 mmio_write_32(lifec[i].reg, lifec[i].val);
332}
333
334/* SRAM/DRAM protection setting */
335static void axi_security_setting(void)
336{
337 uint32_t i;
338
339 for (i = 0; i < ARRAY_SIZE(axi); i++)
340 mmio_write_32(axi[i].reg, axi[i].val);
341}
342
343void bl2_secure_setting(void)
344{
345 const uint32_t delay = 10;
346
347 lifec_security_setting();
348 axi_security_setting();
349 rcar_micro_delay(delay);
350
351 return;
352}