Konstantin Porotchkin | 646b5cc | 2018-06-07 18:48:49 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/debug.h> |
| 10 | #include <drivers/mentor/mi2cv.h> |
| 11 | #include <lib/mmio.h> |
| 12 | |
Konstantin Porotchkin | 646b5cc | 2018-06-07 18:48:49 +0300 | [diff] [blame] | 13 | #include <mv_ddr_if.h> |
| 14 | #include <mvebu_def.h> |
| 15 | #include <plat_marvell.h> |
| 16 | |
| 17 | #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0) |
| 18 | #define MVEBU_AP_MPP_CTRL4_OFFS 16 |
| 19 | #define MVEBU_AP_MPP_CTRL5_OFFS 20 |
| 20 | #define MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA 0x3 |
| 21 | #define MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA 0x3 |
| 22 | |
| 23 | #define MVEBU_CP_MPP_CTRL37_OFFS 20 |
| 24 | #define MVEBU_CP_MPP_CTRL38_OFFS 24 |
| 25 | #define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2 |
| 26 | #define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2 |
| 27 | |
| 28 | #define MVEBU_MPP_CTRL_MASK 0xf |
| 29 | |
| 30 | /* |
| 31 | * This struct provides the DRAM training code with |
| 32 | * the appropriate board DRAM configuration |
| 33 | */ |
| 34 | static struct mv_ddr_topology_map board_topology_map = { |
| 35 | /* MISL board with 1CS 8Gb x4 devices of Micron 2400T */ |
| 36 | DEBUG_LEVEL_ERROR, |
| 37 | 0x1, /* active interfaces */ |
| 38 | /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ |
| 39 | { { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */ |
| 40 | {0x1, 0x0, 0, 0}, |
| 41 | {0x1, 0x0, 0, 0}, |
| 42 | {0x1, 0x0, 0, 0}, |
| 43 | {0x1, 0x0, 0, 0}, |
| 44 | {0x1, 0x0, 0, 0}, |
| 45 | {0x1, 0x0, 0, 0}, |
| 46 | {0x1, 0x0, 0, 0}, |
| 47 | {0x1, 0x0, 0, 0} }, |
| 48 | /* TODO: double check if the speed bin is 2400T */ |
| 49 | SPEED_BIN_DDR_2400T, /* speed_bin */ |
| 50 | MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ |
| 51 | MV_DDR_DIE_CAP_8GBIT, /* die capacity */ |
| 52 | MV_DDR_FREQ_SAR, /* frequency */ |
| 53 | 0, 0, /* cas_l, cas_wl */ |
| 54 | MV_DDR_TEMP_LOW} }, /* temperature */ |
| 55 | MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ |
| 56 | MV_DDR_CFG_SPD, /* ddr configuration data source */ |
| 57 | { {0} }, /* raw spd data */ |
| 58 | {0}, /* timing parameters */ |
| 59 | { /* electrical configuration */ |
| 60 | { /* memory electrical configuration */ |
| 61 | MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ |
| 62 | { |
| 63 | MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ |
| 64 | MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ |
| 65 | }, |
| 66 | { |
| 67 | MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ |
| 68 | MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */ |
| 69 | }, |
| 70 | MV_DDR_DIC_RZQ_DIV7 /* dic */ |
| 71 | }, |
| 72 | { /* phy electrical configuration */ |
| 73 | MV_DDR_OHM_30, /* data_drv_p */ |
| 74 | MV_DDR_OHM_30, /* data_drv_n */ |
| 75 | MV_DDR_OHM_30, /* ctrl_drv_p */ |
| 76 | MV_DDR_OHM_30, /* ctrl_drv_n */ |
| 77 | { |
| 78 | MV_DDR_OHM_60, /* odt_p 1cs */ |
| 79 | MV_DDR_OHM_120 /* odt_p 2cs */ |
| 80 | }, |
| 81 | { |
| 82 | MV_DDR_OHM_60, /* odt_n 1cs */ |
| 83 | MV_DDR_OHM_120 /* odt_n 2cs */ |
| 84 | }, |
| 85 | }, |
| 86 | { /* mac electrical configuration */ |
| 87 | MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ |
| 88 | MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ |
| 89 | MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ |
| 90 | }, |
| 91 | } |
| 92 | }; |
| 93 | |
| 94 | struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) |
| 95 | { |
| 96 | /* Return the board topology as defined in the board code */ |
| 97 | return &board_topology_map; |
| 98 | } |
| 99 | |
| 100 | static void mpp_config(void) |
| 101 | { |
| 102 | uintptr_t reg; |
| 103 | uint32_t val; |
| 104 | |
| 105 | reg = MVEBU_CP_MPP_REGS(0, 4); |
| 106 | /* configure CP0 MPP 37 and 38 to i2c */ |
| 107 | val = mmio_read_32(reg); |
| 108 | val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) | |
| 109 | (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS)); |
| 110 | val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA << |
| 111 | MVEBU_CP_MPP_CTRL37_OFFS) | |
| 112 | (MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA << |
| 113 | MVEBU_CP_MPP_CTRL38_OFFS); |
| 114 | mmio_write_32(reg, val); |
| 115 | } |
| 116 | |
| 117 | /* |
| 118 | * This function may modify the default DRAM parameters |
| 119 | * based on information received from SPD or bootloader |
| 120 | * configuration located on non volatile storage |
| 121 | */ |
| 122 | void plat_marvell_dram_update_topology(void) |
| 123 | { |
| 124 | struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); |
| 125 | |
| 126 | INFO("Gathering DRAM information\n"); |
| 127 | |
| 128 | if (tm->cfg_src == MV_DDR_CFG_SPD) { |
| 129 | /* configure MPPs to enable i2c */ |
| 130 | mpp_config(); |
| 131 | |
| 132 | /* initialize i2c */ |
| 133 | i2c_init((void *)MVEBU_CP0_I2C_BASE); |
| 134 | |
| 135 | /* select SPD memory page 0 to access DRAM configuration */ |
| 136 | i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1); |
| 137 | |
| 138 | /* read data from spd */ |
| 139 | i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes, |
| 140 | sizeof(tm->spd_data.all_bytes)); |
| 141 | } |
| 142 | } |