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Antonio Nino Diazae6779e2017-11-06 14:49:04 +00001/*
Antonio Nino Diaz1f470022018-03-27 09:39:47 +01002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl_common.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000010#include <debug.h>
11#include <desc_image_load.h>
12#include <platform_def.h>
13#include <xlat_mmu_helpers.h>
14#include <xlat_tables_defs.h>
15
16#include "rpi3_private.h"
17
18/* Data structure which holds the extents of the trusted SRAM for BL2 */
19static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
20
21/*******************************************************************************
22 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
23 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
24 * Copy it to a safe location before its reclaimed by later BL2 functionality.
25 ******************************************************************************/
26void bl2_early_platform_setup(meminfo_t *mem_layout)
27{
28 /* Initialize the console to provide early debug support */
Antonio Nino Diaz1f470022018-03-27 09:39:47 +010029 rpi3_console_init();
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000030
31 /* Setup the BL2 memory layout */
32 bl2_tzram_layout = *mem_layout;
33
34 plat_rpi3_io_setup();
35}
36
37void bl2_platform_setup(void)
38{
39 /*
40 * This is where a TrustZone address space controller and other
Antonio Nino Diaz1f470022018-03-27 09:39:47 +010041 * security related peripherals would be configured.
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000042 */
43}
44
45/*******************************************************************************
46 * Perform the very early platform specific architectural setup here.
47 ******************************************************************************/
48void bl2_plat_arch_setup(void)
49{
50 rpi3_setup_page_tables(bl2_tzram_layout.total_base,
51 bl2_tzram_layout.total_size,
52 BL_CODE_BASE, BL_CODE_END,
53 BL_RO_DATA_BASE, BL_RO_DATA_END
54#if USE_COHERENT_MEM
55 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
56#endif
57 );
58
59 enable_mmu_el1(0);
60}
61
62/*******************************************************************************
63 * This function can be used by the platforms to update/use image
64 * information for given `image_id`.
65 ******************************************************************************/
66int bl2_plat_handle_post_image_load(unsigned int image_id)
67{
68 int err = 0;
69 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
70
71 assert(bl_mem_params != NULL);
72
73 switch (image_id) {
74 case BL32_IMAGE_ID:
75 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry();
76 break;
77
78 case BL33_IMAGE_ID:
79 /* BL33 expects to receive the primary CPU MPID (through r0) */
80 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
81 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
82 break;
83
Jonathan Wrightff957ed2018-03-14 15:24:00 +000084 default:
85 /* Do nothing in default case */
86 break;
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000087 }
88
89 return err;
90}