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Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Boyan Karatotev192ad5d2023-12-12 15:59:01 +00002 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <plat/arm/common/plat_arm.h>
8#include <plat/arm/css/common/css_pm.h>
Boyan Karatotev192ad5d2023-12-12 15:59:01 +00009#include <platform_def.h>
Usama Arifbec5afd2020-04-17 16:13:39 +010010
11/******************************************************************************
12 * The power domain tree descriptor.
13 ******************************************************************************/
Usama Ariff1513622021-04-09 17:07:41 +010014const unsigned char tc_pd_tree_desc[] = {
Usama Arifbec5afd2020-04-17 16:13:39 +010015 PLAT_ARM_CLUSTER_COUNT,
16 PLAT_MAX_CPUS_PER_CLUSTER,
17};
18
19/*******************************************************************************
20 * This function returns the topology tree information.
21 ******************************************************************************/
22const unsigned char *plat_get_power_domain_tree_desc(void)
23{
Usama Ariff1513622021-04-09 17:07:41 +010024 return tc_pd_tree_desc;
Usama Arifbec5afd2020-04-17 16:13:39 +010025}
26
27/*******************************************************************************
28 * The array mapping platform core position (implemented by plat_my_core_pos())
29 * to the SCMI power domain ID implemented by SCP.
30 ******************************************************************************/
31const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
32 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
33 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
34 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
35 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
36 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
Avinash Mehtaf68a0842020-10-28 16:43:28 +000037 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
38 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
39 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
Boyan Karatotev192ad5d2023-12-12 15:59:01 +000040#if PLATFORM_CORE_COUNT == 14
41 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
42 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
43 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
44 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
45 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
46 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
47#endif /* PLATFORM_CORE_COUNT == 14 */
Usama Arifbec5afd2020-04-17 16:13:39 +010048};
49
50/*******************************************************************************
51 * This function returns the core count within the cluster corresponding to
52 * `mpidr`.
53 ******************************************************************************/
54unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
55{
56 return PLAT_MAX_CPUS_PER_CLUSTER;
57}
58
59#if ARM_PLAT_MT
60/******************************************************************************
61 * Return the number of PE's supported by the CPU.
62 *****************************************************************************/
63unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
64{
65 return PLAT_MAX_PE_PER_CPU;
66}
67#endif