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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew981487a2015-07-13 14:10:57 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
34#include <bl_common.h>
35#include <context.h>
Achin Guptaef7a28c2014-02-01 08:59:56 +000036#include <context_mgmt.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010037#include <platform.h>
38#include <stddef.h>
Dan Handley714a0d22014-04-09 13:13:04 +010039#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
Achin Guptaef7a28c2014-02-01 08:59:56 +000042 * Per cpu non-secure contexts used to program the architectural state prior
43 * return to the normal world.
44 * TODO: Use the memory allocator to set aside memory for the contexts instead
Soby Mathew981487a2015-07-13 14:10:57 +010045 * of relying on platform defined constants.
Achin Guptaef7a28c2014-02-01 08:59:56 +000046 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +010047static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
Achin Guptaef7a28c2014-02-01 08:59:56 +000048
Soby Mathew6cdddaf2015-01-07 11:10:22 +000049/******************************************************************************
50 * Define the psci capability variable.
51 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010052unsigned int psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +000053
Dan Handley60b13e32014-05-14 15:13:16 +010054/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010055 * Function which initializes the 'psci_non_cpu_pd_nodes' or the
56 * 'psci_cpu_pd_nodes' corresponding to the power level.
Achin Gupta4f6ad662013-10-25 09:08:21 +010057 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010058static void psci_init_pwr_domain_node(unsigned int node_idx,
59 unsigned int parent_idx,
60 unsigned int level)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061{
Soby Mathew981487a2015-07-13 14:10:57 +010062 if (level > PSCI_CPU_PWR_LVL) {
63 psci_non_cpu_pd_nodes[node_idx].level = level;
64 psci_lock_init(psci_non_cpu_pd_nodes, node_idx);
65 psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx;
66 psci_non_cpu_pd_nodes[node_idx].local_state =
67 PLAT_MAX_OFF_STATE;
68 } else {
69 psci_cpu_data_t *svc_cpu_data;
Achin Gupta4f6ad662013-10-25 09:08:21 +010070
Soby Mathew981487a2015-07-13 14:10:57 +010071 psci_cpu_pd_nodes[node_idx].parent_node = parent_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +010072
Soby Mathew981487a2015-07-13 14:10:57 +010073 /* Initialize with an invalid mpidr */
74 psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR;
Soby Mathew2b697502014-10-02 17:24:19 +010075
Soby Mathew981487a2015-07-13 14:10:57 +010076 svc_cpu_data =
77 &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data);
Soby Mathew2b697502014-10-02 17:24:19 +010078
Soby Mathew981487a2015-07-13 14:10:57 +010079 /* Set the Affinity Info for the cores as OFF */
80 svc_cpu_data->aff_info_state = AFF_STATE_OFF;
Achin Gupta4f6ad662013-10-25 09:08:21 +010081
Soby Mathew981487a2015-07-13 14:10:57 +010082 /* Invalidate the suspend level for the cpu */
Soby Mathew011ca182015-07-29 17:05:03 +010083 svc_cpu_data->target_pwrlvl = PSCI_INVALID_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +010084
Soby Mathew981487a2015-07-13 14:10:57 +010085 /* Set the power state to OFF state */
86 svc_cpu_data->local_state = PLAT_MAX_OFF_STATE;
Soby Mathew2b697502014-10-02 17:24:19 +010087
Soby Mathew011ca182015-07-29 17:05:03 +010088 flush_dcache_range((uintptr_t)svc_cpu_data,
Soby Mathew981487a2015-07-13 14:10:57 +010089 sizeof(*svc_cpu_data));
Achin Gupta4f6ad662013-10-25 09:08:21 +010090
Soby Mathew981487a2015-07-13 14:10:57 +010091 cm_set_context_by_index(node_idx,
92 (void *) &psci_ns_context[node_idx],
93 NON_SECURE);
94 }
Achin Gupta4f6ad662013-10-25 09:08:21 +010095}
96
97/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010098 * This functions updates cpu_start_idx and ncpus field for each of the node in
99 * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of
100 * the CPUs and check whether they match with the parent of the previous
101 * CPU. The basic assumption for this work is that children of the same parent
102 * are allocated adjacent indices. The platform should ensure this though proper
103 * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and
104 * plat_my_core_pos() APIs.
105 *******************************************************************************/
106static void psci_update_pwrlvl_limits(void)
Achin Gupta0959db52013-12-02 17:33:04 +0000107{
Soby Mathew011ca182015-07-29 17:05:03 +0100108 int j;
Soby Mathew981487a2015-07-13 14:10:57 +0100109 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
Soby Mathew011ca182015-07-29 17:05:03 +0100110 unsigned int temp_index[PLAT_MAX_PWR_LVL], cpu_idx;
Achin Gupta0959db52013-12-02 17:33:04 +0000111
Soby Mathew981487a2015-07-13 14:10:57 +0100112 for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
113 psci_get_parent_pwr_domain_nodes(cpu_idx,
114 PLAT_MAX_PWR_LVL,
115 temp_index);
116 for (j = PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
117 if (temp_index[j] != nodes_idx[j]) {
118 nodes_idx[j] = temp_index[j];
119 psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx
120 = cpu_idx;
Achin Gupta0959db52013-12-02 17:33:04 +0000121 }
Soby Mathew981487a2015-07-13 14:10:57 +0100122 psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++;
123 }
Achin Gupta0959db52013-12-02 17:33:04 +0000124 }
Achin Gupta0959db52013-12-02 17:33:04 +0000125}
126
127/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100128 * Core routine to populate the power domain tree. The tree descriptor passed by
129 * the platform is populated breadth-first and the first entry in the map
130 * informs the number of root power domains. The parent nodes of the root nodes
131 * will point to an invalid entry(-1).
Achin Gupta4f6ad662013-10-25 09:08:21 +0100132 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100133static void populate_power_domain_tree(const unsigned char *topology)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100134{
Soby Mathew981487a2015-07-13 14:10:57 +0100135 unsigned int i, j = 0, num_nodes_at_lvl = 1, num_nodes_at_next_lvl;
136 unsigned int node_index = 0, parent_node_index = 0, num_children;
137 int level = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100138
139 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100140 * For each level the inputs are:
141 * - number of nodes at this level in plat_array i.e. num_nodes_at_level
142 * This is the sum of values of nodes at the parent level.
143 * - Index of first entry at this level in the plat_array i.e.
144 * parent_node_index.
145 * - Index of first free entry in psci_non_cpu_pd_nodes[] or
146 * psci_cpu_pd_nodes[] i.e. node_index depending upon the level.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147 */
Soby Mathew981487a2015-07-13 14:10:57 +0100148 while (level >= PSCI_CPU_PWR_LVL) {
149 num_nodes_at_next_lvl = 0;
Achin Guptaef7a28c2014-02-01 08:59:56 +0000150 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100151 * For each entry (parent node) at this level in the plat_array:
152 * - Find the number of children
153 * - Allocate a node in a power domain array for each child
154 * - Set the parent of the child to the parent_node_index - 1
155 * - Increment parent_node_index to point to the next parent
156 * - Accumulate the number of children at next level.
Achin Guptaef7a28c2014-02-01 08:59:56 +0000157 */
Soby Mathew981487a2015-07-13 14:10:57 +0100158 for (i = 0; i < num_nodes_at_lvl; i++) {
159 assert(parent_node_index <=
160 PSCI_NUM_NON_CPU_PWR_DOMAINS);
161 num_children = topology[parent_node_index];
Achin Guptaef7a28c2014-02-01 08:59:56 +0000162
Soby Mathew981487a2015-07-13 14:10:57 +0100163 for (j = node_index;
164 j < node_index + num_children; j++)
165 psci_init_pwr_domain_node(j,
166 parent_node_index - 1,
167 level);
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100168
Soby Mathew981487a2015-07-13 14:10:57 +0100169 node_index = j;
170 num_nodes_at_next_lvl += num_children;
171 parent_node_index++;
172 }
Achin Guptaf6b9e992014-07-31 11:19:11 +0100173
Soby Mathew981487a2015-07-13 14:10:57 +0100174 num_nodes_at_lvl = num_nodes_at_next_lvl;
175 level--;
Soby Mathew7d861ea2014-11-18 10:14:14 +0000176
Soby Mathew981487a2015-07-13 14:10:57 +0100177 /* Reset the index for the cpu power domain array */
178 if (level == PSCI_CPU_PWR_LVL)
179 node_index = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100180 }
181
Soby Mathew981487a2015-07-13 14:10:57 +0100182 /* Validate the sanity of array exported by the platform */
183 assert(j == PLATFORM_CORE_COUNT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184}
185
186/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100187 * This function initializes the power domain topology tree by querying the
188 * platform. The power domain nodes higher than the CPU are populated in the
189 * array psci_non_cpu_pd_nodes[] and the CPU power domains are populated in
190 * psci_cpu_pd_nodes[]. The platform exports its static topology map through the
191 * populate_power_domain_topology_tree() API. The algorithm populates the
192 * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this
193 * topology map. On a platform that implements two clusters of 2 cpus each, and
194 * supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would look
195 * like this:
Achin Gupta4f6ad662013-10-25 09:08:21 +0100196 *
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197 * ---------------------------------------------------
Soby Mathew981487a2015-07-13 14:10:57 +0100198 * | system node | cluster 0 node | cluster 1 node |
Achin Gupta4f6ad662013-10-25 09:08:21 +0100199 * ---------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200 *
Soby Mathew981487a2015-07-13 14:10:57 +0100201 * And populated psci_cpu_pd_nodes would look like this :
202 * <- cpus cluster0 -><- cpus cluster1 ->
203 * ------------------------------------------------
204 * | CPU 0 | CPU 1 | CPU 2 | CPU 3 |
205 * ------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100207int psci_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208{
Soby Mathew981487a2015-07-13 14:10:57 +0100209 const unsigned char *topology_tree;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210
Soby Mathew981487a2015-07-13 14:10:57 +0100211 /* Query the topology map from the platform */
212 topology_tree = plat_get_power_domain_tree_desc();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100213
Soby Mathew981487a2015-07-13 14:10:57 +0100214 /* Populate the power domain arrays using the platform topology map */
215 populate_power_domain_tree(topology_tree);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216
Soby Mathew981487a2015-07-13 14:10:57 +0100217 /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
218 psci_update_pwrlvl_limits();
219
220 /* Populate the mpidr field of cpu node for this CPU */
221 psci_cpu_pd_nodes[plat_my_core_pos()].mpidr =
222 read_mpidr() & MPIDR_AFFINITY_MASK;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100223
Soby Mathew981487a2015-07-13 14:10:57 +0100224 psci_init_req_local_pwr_states();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225
226 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100227 * Set the requested and target state of this CPU and all the higher
228 * power domain levels for this CPU to run.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229 */
Soby Mathew981487a2015-07-13 14:10:57 +0100230 psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100231
Soby Mathew981487a2015-07-13 14:10:57 +0100232 plat_setup_psci_ops((uintptr_t)psci_entrypoint,
233 &psci_plat_pm_ops);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100234 assert(psci_plat_pm_ops);
235
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000236 /* Initialize the psci capability */
237 psci_caps = PSCI_GENERIC_CAP;
238
Soby Mathew981487a2015-07-13 14:10:57 +0100239 if (psci_plat_pm_ops->pwr_domain_off)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000240 psci_caps |= define_psci_cap(PSCI_CPU_OFF);
Soby Mathew981487a2015-07-13 14:10:57 +0100241 if (psci_plat_pm_ops->pwr_domain_on &&
242 psci_plat_pm_ops->pwr_domain_on_finish)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000243 psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64);
Soby Mathew981487a2015-07-13 14:10:57 +0100244 if (psci_plat_pm_ops->pwr_domain_suspend &&
245 psci_plat_pm_ops->pwr_domain_suspend_finish) {
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000246 psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
Soby Mathew96168382014-12-17 14:47:57 +0000247 if (psci_plat_pm_ops->get_sys_suspend_power_state)
248 psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);
249 }
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000250 if (psci_plat_pm_ops->system_off)
251 psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF);
252 if (psci_plat_pm_ops->system_reset)
253 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET);
254
Achin Gupta7421b462014-02-01 18:53:26 +0000255 return 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100256}