| Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <drivers/arm/gicv3.h> |
| Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 10 | #include <platform_def.h> |
| 11 | |
| 12 | .globl plat_secondary_cold_boot_setup |
| 13 | .globl plat_is_my_cpu_primary |
| 14 | .globl versal_calc_core_pos |
| 15 | .globl platform_mem_init |
| 16 | .globl plat_my_core_pos |
| 17 | |
| 18 | /* ----------------------------------------------------- |
| 19 | * void plat_secondary_cold_boot_setup (void); |
| 20 | * |
| 21 | * This function performs any platform specific actions |
| 22 | * needed for a secondary cpu after a cold reset e.g |
| 23 | * mark the cpu's presence, mechanism to place it in a |
| 24 | * holding pen etc. |
| 25 | * TODO: Should we read the PSYS register to make sure |
| 26 | * that the request has gone through. |
| 27 | * ----------------------------------------------------- |
| 28 | */ |
| 29 | func plat_secondary_cold_boot_setup |
| 30 | mrs x0, mpidr_el1 |
| 31 | |
| 32 | /* |
| 33 | * There is no sane reason to come out of this wfi. This |
| 34 | * cpu will be powered on and reset by the cpu_on pm api |
| 35 | */ |
| 36 | dsb sy |
| 37 | bl plat_panic_handler |
| 38 | endfunc plat_secondary_cold_boot_setup |
| 39 | |
| 40 | func plat_is_my_cpu_primary |
| 41 | mov x9, x30 |
| 42 | bl plat_my_core_pos |
| 43 | cmp x0, #VERSAL_PRIMARY_CPU |
| 44 | cset x0, eq |
| 45 | ret x9 |
| 46 | endfunc plat_is_my_cpu_primary |
| 47 | |
| 48 | /* ----------------------------------------------------- |
| 49 | * unsigned int plat_my_core_pos(void) |
| 50 | * This function uses the versal_calc_core_pos() |
| 51 | * definition to get the index of the calling CPU. |
| 52 | * ----------------------------------------------------- |
| 53 | */ |
| 54 | func plat_my_core_pos |
| 55 | mrs x0, mpidr_el1 |
| 56 | b versal_calc_core_pos |
| 57 | endfunc plat_my_core_pos |
| 58 | |
| 59 | func versal_calc_core_pos |
| 60 | and x1, x0, #MPIDR_CPU_MASK |
| 61 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 62 | add x0, x1, x0, LSR #6 |
| 63 | ret |
| 64 | endfunc versal_calc_core_pos |
| 65 | |
| 66 | /* --------------------------------------------------------------------- |
| 67 | * We don't need to carry out any memory initialization on VERSAL |
| 68 | * platform. The Secure RAM is accessible straight away. |
| 69 | * --------------------------------------------------------------------- |
| 70 | */ |
| 71 | func platform_mem_init |
| 72 | ret |
| 73 | endfunc platform_mem_init |