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Soby Mathew748be1d2016-05-05 14:10:46 +01001/*
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +01002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathew748be1d2016-05-05 14:10:46 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew748be1d2016-05-05 14:10:46 +01005 */
6#include <aem_generic.h>
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <cpu_macros.S>
11
12func aem_generic_core_pwr_dwn
13 /* Assert if cache is enabled */
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +010014#if ENABLE_ASSERTIONS
Soby Mathew748be1d2016-05-05 14:10:46 +010015 ldcopr r0, SCTLR
16 tst r0, #SCTLR_C_BIT
17 ASM_ASSERT(eq)
18#endif
19 /* ---------------------------------------------
20 * Flush L1 cache to PoU.
21 * ---------------------------------------------
22 */
23 mov r0, #DC_OP_CISW
24 b dcsw_op_louis
25endfunc aem_generic_core_pwr_dwn
26
27
28func aem_generic_cluster_pwr_dwn
29 /* Assert if cache is enabled */
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +010030#if ENABLE_ASSERTIONS
Soby Mathew748be1d2016-05-05 14:10:46 +010031 ldcopr r0, SCTLR
32 tst r0, #SCTLR_C_BIT
33 ASM_ASSERT(eq)
34#endif
35 /* ---------------------------------------------
36 * Flush L1 and L2 caches to PoC.
37 * ---------------------------------------------
38 */
39 mov r0, #DC_OP_CISW
40 b dcsw_op_all
41endfunc aem_generic_cluster_pwr_dwn
42
Soby Mathew0980dce2018-09-17 04:34:35 +010043#if REPORT_ERRATA
44/*
45 * Errata printing function for AEM. Must follow AAPCS.
46 */
47func aem_generic_errata_report
48 bx lr
49endfunc aem_generic_errata_report
50#endif
51
Soby Mathew748be1d2016-05-05 14:10:46 +010052/* cpu_ops for Base AEM FVP */
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000053declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \
54 aem_generic_core_pwr_dwn, \
55 aem_generic_cluster_pwr_dwn