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Soby Mathewe063d3c2015-10-07 09:45:27 +01001/*
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +01002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathewe063d3c2015-10-07 09:45:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewe063d3c2015-10-07 09:45:27 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef GICV2_H
8#define GICV2_H
Soby Mathewe063d3c2015-10-07 09:45:27 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <drivers/arm/gic_common.h>
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +010011
Soby Mathewe063d3c2015-10-07 09:45:27 +010012/*******************************************************************************
13 * GICv2 miscellaneous definitions
14 ******************************************************************************/
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010015
16/* Interrupt group definitions */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010017#define GICV2_INTR_GROUP0 U(0)
18#define GICV2_INTR_GROUP1 U(1)
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010019
Soby Mathewe063d3c2015-10-07 09:45:27 +010020/* Interrupt IDs reported by the HPPIR and IAR registers */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010021#define PENDING_G1_INTID U(1022)
Soby Mathewe063d3c2015-10-07 09:45:27 +010022
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +010023/* GICv2 can only target up to 8 PEs */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010024#define GICV2_MAX_TARGET_PE U(8)
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +010025
Soby Mathewe063d3c2015-10-07 09:45:27 +010026/*******************************************************************************
27 * GICv2 specific Distributor interface register offsets and constants.
28 ******************************************************************************/
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010029#define GICD_ITARGETSR U(0x800)
30#define GICD_SGIR U(0xF00)
31#define GICD_CPENDSGIR U(0xF10)
32#define GICD_SPENDSGIR U(0xF20)
33#define GICD_PIDR2_GICV2 U(0xFE8)
Soby Mathewe063d3c2015-10-07 09:45:27 +010034
35#define ITARGETSR_SHIFT 2
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010036#define GIC_TARGET_CPU_MASK U(0xff)
Soby Mathewe063d3c2015-10-07 09:45:27 +010037
38#define CPENDSGIR_SHIFT 2
39#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
40
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010041#define SGIR_TGTLSTFLT_SHIFT 24
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010042#define SGIR_TGTLSTFLT_MASK U(0x3)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010043#define SGIR_TGTLST_SHIFT 16
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010044#define SGIR_TGTLST_MASK U(0xff)
45#define SGIR_INTID_MASK ULL(0xf)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010046
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010047#define SGIR_TGT_SPECIFIC U(0)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010048
49#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \
50 ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \
51 (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \
52 ((intid) & SGIR_INTID_MASK))
53
Soby Mathewe063d3c2015-10-07 09:45:27 +010054/*******************************************************************************
55 * GICv2 specific CPU interface register offsets and constants.
56 ******************************************************************************/
57/* Physical CPU Interface registers */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010058#define GICC_CTLR U(0x0)
59#define GICC_PMR U(0x4)
60#define GICC_BPR U(0x8)
61#define GICC_IAR U(0xC)
62#define GICC_EOIR U(0x10)
63#define GICC_RPR U(0x14)
64#define GICC_HPPIR U(0x18)
65#define GICC_AHPPIR U(0x28)
66#define GICC_IIDR U(0xFC)
67#define GICC_DIR U(0x1000)
Soby Mathewe063d3c2015-10-07 09:45:27 +010068#define GICC_PRIODROP GICC_EOIR
69
70/* GICC_CTLR bit definitions */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010071#define EOI_MODE_NS BIT_32(10)
72#define EOI_MODE_S BIT_32(9)
73#define IRQ_BYP_DIS_GRP1 BIT_32(8)
74#define FIQ_BYP_DIS_GRP1 BIT_32(7)
75#define IRQ_BYP_DIS_GRP0 BIT_32(6)
76#define FIQ_BYP_DIS_GRP0 BIT_32(5)
77#define CBPR BIT_32(4)
Soby Mathewe063d3c2015-10-07 09:45:27 +010078#define FIQ_EN_SHIFT 3
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010079#define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT)
80#define ACK_CTL BIT_32(2)
Soby Mathewe063d3c2015-10-07 09:45:27 +010081
82/* GICC_IIDR bit masks and shifts */
83#define GICC_IIDR_PID_SHIFT 20
84#define GICC_IIDR_ARCH_SHIFT 16
85#define GICC_IIDR_REV_SHIFT 12
86#define GICC_IIDR_IMP_SHIFT 0
87
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010088#define GICC_IIDR_PID_MASK U(0xfff)
89#define GICC_IIDR_ARCH_MASK U(0xf)
90#define GICC_IIDR_REV_MASK U(0xf)
91#define GICC_IIDR_IMP_MASK U(0xfff)
Soby Mathewe063d3c2015-10-07 09:45:27 +010092
93/* HYP view virtual CPU Interface registers */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010094#define GICH_CTL U(0x0)
95#define GICH_VTR U(0x4)
96#define GICH_ELRSR0 U(0x30)
97#define GICH_ELRSR1 U(0x34)
98#define GICH_APR0 U(0xF0)
99#define GICH_LR_BASE U(0x100)
Soby Mathewe063d3c2015-10-07 09:45:27 +0100100
101/* Virtual CPU Interface registers */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100102#define GICV_CTL U(0x0)
103#define GICV_PRIMASK U(0x4)
104#define GICV_BP U(0x8)
105#define GICV_INTACK U(0xC)
106#define GICV_EOI U(0x10)
107#define GICV_RUNNINGPRI U(0x14)
108#define GICV_HIGHESTPEND U(0x18)
109#define GICV_DEACTIVATE U(0x1000)
Soby Mathewe063d3c2015-10-07 09:45:27 +0100110
111/* GICD_CTLR bit definitions */
112#define CTLR_ENABLE_G1_SHIFT 1
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100113#define CTLR_ENABLE_G1_MASK U(0x1)
114#define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT)
Soby Mathewe063d3c2015-10-07 09:45:27 +0100115
116/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100117#define INT_ID_MASK U(0x3ff)
Soby Mathewe063d3c2015-10-07 09:45:27 +0100118
Julius Werner53456fc2019-07-09 13:49:11 -0700119#ifndef __ASSEMBLER__
Soby Mathewe063d3c2015-10-07 09:45:27 +0100120
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +0100121#include <cdefs.h>
Soby Mathewe063d3c2015-10-07 09:45:27 +0100122#include <stdint.h>
123
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000124#include <common/interrupt_props.h>
125
Soby Mathewe063d3c2015-10-07 09:45:27 +0100126/*******************************************************************************
127 * This structure describes some of the implementation defined attributes of
128 * the GICv2 IP. It is used by the platform port to specify these attributes
129 * in order to initialize the GICv2 driver. The attributes are described
130 * below.
131 *
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100132 * The 'gicd_base' field contains the base address of the Distributor interface
133 * programmer's view.
Soby Mathewe063d3c2015-10-07 09:45:27 +0100134 *
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100135 * The 'gicc_base' field contains the base address of the CPU Interface
136 * programmer's view.
Soby Mathewe063d3c2015-10-07 09:45:27 +0100137 *
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100138 * The 'target_masks' is a pointer to an array containing 'target_masks_num'
139 * elements. The GIC driver will populate the array with per-PE target mask to
140 * use to when targeting interrupts.
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100141 *
142 * The 'interrupt_props' field is a pointer to an array that enumerates secure
143 * interrupts and their properties. If this field is not NULL, both
144 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
145 *
146 * The 'interrupt_props_num' field contains the number of entries in the
147 * 'interrupt_props' array. If this field is non-zero, 'g0_interrupt_num' is
148 * ignored.
Soby Mathewe063d3c2015-10-07 09:45:27 +0100149 ******************************************************************************/
150typedef struct gicv2_driver_data {
151 uintptr_t gicd_base;
152 uintptr_t gicc_base;
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100153 unsigned int *target_masks;
154 unsigned int target_masks_num;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100155 const interrupt_prop_t *interrupt_props;
156 unsigned int interrupt_props_num;
Soby Mathewe063d3c2015-10-07 09:45:27 +0100157} gicv2_driver_data_t;
158
159/*******************************************************************************
160 * Function prototypes
161 ******************************************************************************/
162void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data);
163void gicv2_distif_init(void);
164void gicv2_pcpu_distif_init(void);
165void gicv2_cpuif_enable(void);
166void gicv2_cpuif_disable(void);
167unsigned int gicv2_is_fiq_enabled(void);
168unsigned int gicv2_get_pending_interrupt_type(void);
169unsigned int gicv2_get_pending_interrupt_id(void);
170unsigned int gicv2_acknowledge_interrupt(void);
171void gicv2_end_of_interrupt(unsigned int id);
172unsigned int gicv2_get_interrupt_group(unsigned int id);
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100173unsigned int gicv2_get_running_priority(void);
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100174void gicv2_set_pe_target_mask(unsigned int proc_num);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100175unsigned int gicv2_get_interrupt_active(unsigned int id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100176void gicv2_enable_interrupt(unsigned int id);
177void gicv2_disable_interrupt(unsigned int id);
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100178void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100179void gicv2_set_interrupt_type(unsigned int id, unsigned int type);
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100180void gicv2_raise_sgi(int sgi_num, int proc_num);
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100181void gicv2_set_spi_routing(unsigned int id, int proc_num);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100182void gicv2_set_interrupt_pending(unsigned int id);
183void gicv2_clear_interrupt_pending(unsigned int id);
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100184unsigned int gicv2_set_pmr(unsigned int mask);
Marcin Wojtasdd568dd2018-03-21 09:55:47 +0100185void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
Soby Mathewe063d3c2015-10-07 09:45:27 +0100186
Julius Werner53456fc2019-07-09 13:49:11 -0700187#endif /* __ASSEMBLER__ */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000188#endif /* GICV2_H */