blob: 33f80183c557e9e8c355771367f9e37195af9f69 [file] [log] [blame]
Achin Gupta1fa7eb62015-11-03 14:18:34 +00001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arm_def.h>
32#include <gicv3.h>
33#include <plat_arm.h>
34#include <platform.h>
35#include <platform_def.h>
36
37/******************************************************************************
38 * The following functions are defined as weak to allow a platform to override
39 * the way the GICv3 driver is initialised and used.
40 *****************************************************************************/
41#pragma weak plat_arm_gic_driver_init
42#pragma weak plat_arm_gic_init
43#pragma weak plat_arm_gic_cpuif_enable
44#pragma weak plat_arm_gic_cpuif_disable
45#pragma weak plat_arm_gic_pcpu_init
46
47/* The GICv3 driver only needs to be initialized in EL3 */
48uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
49
50/* Array of Group1 secure interrupts to be configured by the gic driver */
51const unsigned int g1s_interrupt_array[] = {
52 PLAT_ARM_G1S_IRQS
53};
54
55/* Array of Group0 interrupts to be configured by the gic driver */
56const unsigned int g0_interrupt_array[] = {
57 PLAT_ARM_G0_IRQS
58};
59
60const gicv3_driver_data_t arm_gic_data = {
61 .gicd_base = PLAT_ARM_GICD_BASE,
62 .gicr_base = PLAT_ARM_GICR_BASE,
63 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
64 .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
65 .g0_interrupt_array = g0_interrupt_array,
66 .g1s_interrupt_array = g1s_interrupt_array,
67 .rdistif_num = PLATFORM_CORE_COUNT,
68 .rdistif_base_addrs = rdistif_base_addrs,
69 .mpidr_to_core_pos = plat_arm_calc_core_pos
70};
71
72void plat_arm_gic_driver_init(void)
73{
74 /*
75 * The GICv3 driver is initialized in EL3 and does not need
76 * to be initialized again in SEL1. This is because the S-EL1
77 * can use GIC system registers to manage interrupts and does
78 * not need GIC interface base addresses to be configured.
79 */
80#if IMAGE_BL31
81 gicv3_driver_init(&arm_gic_data);
82#endif
83}
84
85/******************************************************************************
86 * ARM common helper to initialize the GIC. Only invoked by BL31
87 *****************************************************************************/
88void plat_arm_gic_init(void)
89{
90 gicv3_distif_init();
91 gicv3_rdistif_init(plat_my_core_pos());
92 gicv3_cpuif_enable(plat_my_core_pos());
93}
94
95/******************************************************************************
96 * ARM common helper to enable the GIC CPU interface
97 *****************************************************************************/
98void plat_arm_gic_cpuif_enable(void)
99{
100 gicv3_cpuif_enable(plat_my_core_pos());
101}
102
103/******************************************************************************
104 * ARM common helper to disable the GIC CPU interface
105 *****************************************************************************/
106void plat_arm_gic_cpuif_disable(void)
107{
108 gicv3_cpuif_disable(plat_my_core_pos());
109}
110
111/******************************************************************************
112 * ARM common helper to initialize the per-cpu redistributor interface in GICv3
113 *****************************************************************************/
114void plat_arm_gic_pcpu_init(void)
115{
116 gicv3_rdistif_init(plat_my_core_pos());
117}