Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 1 | /* |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 7 | #include <common/debug.h> |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 8 | #include <cdefs.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <drivers/arm/smmu_v3.h> |
| 10 | #include <lib/mmio.h> |
| 11 | |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 12 | /* SMMU poll number of retries */ |
| 13 | #define SMMU_POLL_RETRY 1000000 |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 14 | |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 15 | static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, |
| 16 | uint32_t value) |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 17 | { |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 18 | uint32_t reg_val, retries = SMMU_POLL_RETRY; |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 19 | |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 20 | do { |
| 21 | reg_val = mmio_read_32(smmu_reg); |
| 22 | if ((reg_val & mask) == value) |
| 23 | return 0; |
| 24 | } while (--retries != 0U); |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 25 | |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 26 | ERROR("Failed to poll SMMUv3 register @%p\n", (void *)smmu_reg); |
| 27 | ERROR("Read value 0x%x, expected 0x%x\n", reg_val, |
| 28 | value == 0U ? reg_val & ~mask : reg_val | mask); |
| 29 | return -1; |
Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 30 | } |
| 31 | |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 32 | /* |
| 33 | * Initialize the SMMU by invalidating all secure caches and TLBs. |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 34 | * Abort all incoming transactions in order to implement a default |
| 35 | * deny policy on reset |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 36 | */ |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 37 | int __init smmuv3_init(uintptr_t smmu_base) |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 38 | { |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 39 | /* |
| 40 | * Invalidation of secure caches and TLBs is required only if the SMMU |
| 41 | * supports secure state. If not, it's implementation defined as to how |
| 42 | * SMMU_S_INIT register is accessed. |
| 43 | */ |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 44 | if ((mmio_read_32(smmu_base + SMMU_S_IDR1) & |
| 45 | SMMU_S_IDR1_SECURE_IMPL) != 0U) { |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 46 | |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 47 | /* Initiate invalidation */ |
| 48 | mmio_write_32(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL); |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 49 | |
Alexei Fedorov | 6b4a5f0 | 2019-04-26 12:07:07 +0100 | [diff] [blame] | 50 | /* Wait for global invalidation operation to finish */ |
| 51 | return smmuv3_poll(smmu_base + SMMU_S_INIT, |
| 52 | SMMU_S_INIT_INV_ALL, 0U); |
| 53 | } |
Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 54 | return 0; |
| 55 | } |