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git01.mediatek.com / filogic / atf / 930ee2e0fc3892fafa4b718787501aa9c9ba9624 / . / drivers / arm / gic / aarch64 / gic_v3_sysregs.S
blob: 2a96da768637c679d79de6edeb7a4ad64589945e [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Dan Handleye83b0ca2014-01-14 18:17:09 +0000[diff] [blame]2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]31#include <asm_macros.S>
32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]33 .globl read_icc_sre_el1
34 .globl read_icc_sre_el2
35 .globl read_icc_sre_el3
36 .globl write_icc_sre_el1
37 .globl write_icc_sre_el2
38 .globl write_icc_sre_el3
39 .globl write_icc_pmr_el1
40
41
42/*
43 * Register definitions used by GCC for GICv3 access.
44 * These are defined by ARMCC, so keep them in the GCC specific code for now.
45 */
46#define ICC_SRE_EL1 S3_0_C12_C12_5
47#define ICC_SRE_EL2 S3_4_C12_C9_5
48#define ICC_SRE_EL3 S3_6_C12_C12_5
49#define ICC_CTLR_EL1 S3_0_C12_C12_4
50#define ICC_CTLR_EL3 S3_6_C12_C12_4
51#define ICC_PMR_EL1 S3_0_C4_C6_0
52
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]53func read_icc_sre_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]54 mrs x0, ICC_SRE_EL1
55 ret
56
57
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]58func read_icc_sre_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]59 mrs x0, ICC_SRE_EL2
60 ret
61
62
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]63func read_icc_sre_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]64 mrs x0, ICC_SRE_EL3
65 ret
66
67
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]68func write_icc_sre_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]69 msr ICC_SRE_EL1, x0
70 isb
71 ret
72
73
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]74func write_icc_sre_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]75 msr ICC_SRE_EL2, x0
76 isb
77 ret
78
79
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]80func write_icc_sre_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]81 msr ICC_SRE_EL3, x0
82 isb
83 ret
84
85
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]86func write_icc_pmr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]87 msr ICC_PMR_EL1, x0
88 isb
89 ret