| Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 1 | /* |
| Samuel Holland | 38d98de | 2019-02-17 15:10:36 -0600 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
| Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef SUNXI_MMAP_H |
| 8 | #define SUNXI_MMAP_H |
| Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 9 | |
| 10 | /* Memory regions */ |
| 11 | #define SUNXI_ROM_BASE 0x00000000 |
| 12 | #define SUNXI_ROM_SIZE 0x00010000 |
| 13 | #define SUNXI_SRAM_BASE 0x00020000 |
| Andre Przywara | 24b3a1e | 2018-10-16 00:58:22 +0100 | [diff] [blame] | 14 | #define SUNXI_SRAM_SIZE 0x000f8000 |
| Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 15 | #define SUNXI_SRAM_A1_BASE 0x00020000 |
| 16 | #define SUNXI_SRAM_A1_SIZE 0x00008000 |
| Samuel Holland | 38d98de | 2019-02-17 15:10:36 -0600 | [diff] [blame] | 17 | #define SUNXI_SRAM_A2_BASE 0x00100000 |
| Icenowy Zheng | 431b4e8 | 2021-07-23 11:35:24 +0800 | [diff] [blame] | 18 | #define SUNXI_SRAM_A2_BL31_OFFSET 0x00004000 |
| Samuel Holland | 38d98de | 2019-02-17 15:10:36 -0600 | [diff] [blame] | 19 | #define SUNXI_SRAM_A2_SIZE 0x00018000 |
| Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 20 | #define SUNXI_SRAM_C_BASE 0x00028000 |
| 21 | #define SUNXI_SRAM_C_SIZE 0x0001e000 |
| 22 | #define SUNXI_DEV_BASE 0x01000000 |
| 23 | #define SUNXI_DEV_SIZE 0x09000000 |
| 24 | #define SUNXI_DRAM_BASE 0x40000000 |
| Andre Przywara | b3fddff | 2018-09-20 21:13:55 +0100 | [diff] [blame] | 25 | #define SUNXI_DRAM_VIRT_BASE 0x0a000000 |
| Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 26 | |
| 27 | /* Memory-mapped devices */ |
| 28 | #define SUNXI_SYSCON_BASE 0x03000000 |
| 29 | #define SUNXI_CPUCFG_BASE 0x09010000 |
| 30 | #define SUNXI_SID_BASE 0x03006000 |
| 31 | #define SUNXI_DMA_BASE 0x03002000 |
| 32 | #define SUNXI_MSGBOX_BASE 0x03003000 |
| Andre Przywara | d878c48 | 2020-03-17 00:07:31 +0000 | [diff] [blame] | 33 | #define SUNXI_CCU_BASE 0x03001000 |
| Andre Przywara | d878c48 | 2020-03-17 00:07:31 +0000 | [diff] [blame] | 34 | #define SUNXI_PIO_BASE 0x0300b000 |
| Samuel Holland | f93a9ab | 2020-12-13 21:56:15 -0600 | [diff] [blame] | 35 | #define SUNXI_SPC_BASE 0x03008000 |
| Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 36 | #define SUNXI_TIMER_BASE 0x03009000 |
| 37 | #define SUNXI_WDOG_BASE 0x030090a0 |
| 38 | #define SUNXI_THS_BASE 0x05070400 |
| 39 | #define SUNXI_UART0_BASE 0x05000000 |
| 40 | #define SUNXI_UART1_BASE 0x05000400 |
| 41 | #define SUNXI_UART2_BASE 0x05000800 |
| 42 | #define SUNXI_UART3_BASE 0x05000c00 |
| 43 | #define SUNXI_I2C0_BASE 0x05002000 |
| 44 | #define SUNXI_I2C1_BASE 0x05002400 |
| 45 | #define SUNXI_I2C2_BASE 0x05002800 |
| 46 | #define SUNXI_I2C3_BASE 0x05002c00 |
| 47 | #define SUNXI_SPI0_BASE 0x05010000 |
| 48 | #define SUNXI_SPI1_BASE 0x05011000 |
| 49 | #define SUNXI_SCU_BASE 0x03020000 |
| 50 | #define SUNXI_GICD_BASE 0x03021000 |
| 51 | #define SUNXI_GICC_BASE 0x03022000 |
| 52 | #define SUNXI_R_TIMER_BASE 0x07020000 |
| 53 | #define SUNXI_R_INTC_BASE 0x07021000 |
| 54 | #define SUNXI_R_WDOG_BASE 0x07020400 |
| 55 | #define SUNXI_R_PRCM_BASE 0x07010000 |
| 56 | #define SUNXI_R_TWD_BASE 0x07020800 |
| 57 | #define SUNXI_R_CPUCFG_BASE 0x07000400 |
| 58 | #define SUNXI_R_I2C_BASE 0x07081400 |
| Samuel Holland | cb093f2 | 2020-12-13 22:34:10 -0600 | [diff] [blame] | 59 | #define SUNXI_R_RSB_BASE 0x07083000 |
| Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 60 | #define SUNXI_R_UART_BASE 0x07080000 |
| 61 | #define SUNXI_R_PIO_BASE 0x07022000 |
| 62 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 63 | #endif /* SUNXI_MMAP_H */ |