Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 1 | /* |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 2 | * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 7 | #include <assert.h> |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 8 | #include <cdefs.h> |
Antonio Nino Diaz | 033b4bb | 2018-10-25 16:52:26 +0100 | [diff] [blame] | 9 | #include <stdbool.h> |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 10 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <arch.h> |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 12 | #include <arch_features.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <arch_helpers.h> |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 14 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <lib/el3_runtime/pubsub_events.h> |
| 16 | #include <lib/extensions/amu.h> |
| 17 | #include <lib/extensions/amu_private.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 18 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 19 | #include <plat/common/platform.h> |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 20 | |
| 21 | static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT]; |
| 22 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 23 | static inline __unused uint64_t read_id_aa64pfr0_el1_amu(void) |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 24 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 25 | return (read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) & |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 26 | ID_AA64PFR0_AMU_MASK; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 27 | } |
| 28 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 29 | static inline __unused uint64_t read_hcr_el2_amvoffen(void) |
| 30 | { |
| 31 | return (read_hcr_el2() & HCR_AMVOFFEN_BIT) >> |
| 32 | HCR_AMVOFFEN_SHIFT; |
| 33 | } |
| 34 | |
| 35 | static inline __unused void write_cptr_el2_tam(uint64_t value) |
| 36 | { |
| 37 | write_cptr_el2((read_cptr_el2() & ~CPTR_EL2_TAM_BIT) | |
| 38 | ((value << CPTR_EL2_TAM_SHIFT) & CPTR_EL2_TAM_BIT)); |
| 39 | } |
| 40 | |
| 41 | static inline __unused void write_cptr_el3_tam(cpu_context_t *ctx, uint64_t tam) |
| 42 | { |
| 43 | uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); |
| 44 | |
| 45 | value &= ~TAM_BIT; |
| 46 | value |= (tam << TAM_SHIFT) & TAM_BIT; |
| 47 | |
| 48 | write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, value); |
| 49 | } |
| 50 | |
| 51 | static inline __unused void write_hcr_el2_amvoffen(uint64_t value) |
| 52 | { |
| 53 | write_hcr_el2((read_hcr_el2() & ~HCR_AMVOFFEN_BIT) | |
| 54 | ((value << HCR_AMVOFFEN_SHIFT) & HCR_AMVOFFEN_BIT)); |
| 55 | } |
| 56 | |
| 57 | static inline __unused void write_amcr_el0_cg1rz(uint64_t value) |
| 58 | { |
| 59 | write_amcr_el0((read_amcr_el0() & ~AMCR_CG1RZ_BIT) | |
| 60 | ((value << AMCR_CG1RZ_SHIFT) & AMCR_CG1RZ_BIT)); |
| 61 | } |
| 62 | |
| 63 | static inline __unused uint64_t read_amcfgr_el0_ncg(void) |
| 64 | { |
| 65 | return (read_amcfgr_el0() >> AMCFGR_EL0_NCG_SHIFT) & |
| 66 | AMCFGR_EL0_NCG_MASK; |
| 67 | } |
| 68 | |
| 69 | static inline __unused uint64_t read_amcg1idr_el0_voff(void) |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 70 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 71 | return (read_amcg1idr_el0() >> AMCG1IDR_VOFF_SHIFT) & |
| 72 | AMCG1IDR_VOFF_MASK; |
| 73 | } |
| 74 | |
| 75 | static inline __unused uint64_t read_amcgcr_el0_cg1nc(void) |
| 76 | { |
| 77 | return (read_amcgcr_el0() >> AMCGCR_EL0_CG1NC_SHIFT) & |
| 78 | AMCGCR_EL0_CG1NC_MASK; |
| 79 | } |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 80 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 81 | static inline __unused uint64_t read_amcntenset0_el0_px(void) |
| 82 | { |
| 83 | return (read_amcntenset0_el0() >> AMCNTENSET0_EL0_Pn_SHIFT) & |
| 84 | AMCNTENSET0_EL0_Pn_MASK; |
| 85 | } |
| 86 | |
| 87 | static inline __unused uint64_t read_amcntenset1_el0_px(void) |
| 88 | { |
| 89 | return (read_amcntenset1_el0() >> AMCNTENSET1_EL0_Pn_SHIFT) & |
| 90 | AMCNTENSET1_EL0_Pn_MASK; |
| 91 | } |
| 92 | |
| 93 | static inline __unused void write_amcntenset0_el0_px(uint64_t px) |
| 94 | { |
| 95 | uint64_t value = read_amcntenset0_el0(); |
| 96 | |
| 97 | value &= ~AMCNTENSET0_EL0_Pn_MASK; |
| 98 | value |= (px << AMCNTENSET0_EL0_Pn_SHIFT) & AMCNTENSET0_EL0_Pn_MASK; |
| 99 | |
| 100 | write_amcntenset0_el0(value); |
| 101 | } |
| 102 | |
| 103 | static inline __unused void write_amcntenset1_el0_px(uint64_t px) |
| 104 | { |
| 105 | uint64_t value = read_amcntenset1_el0(); |
| 106 | |
| 107 | value &= ~AMCNTENSET1_EL0_Pn_MASK; |
| 108 | value |= (px << AMCNTENSET1_EL0_Pn_SHIFT) & AMCNTENSET1_EL0_Pn_MASK; |
| 109 | |
| 110 | write_amcntenset1_el0(value); |
| 111 | } |
| 112 | |
| 113 | static inline __unused void write_amcntenclr0_el0_px(uint64_t px) |
| 114 | { |
| 115 | uint64_t value = read_amcntenclr0_el0(); |
| 116 | |
| 117 | value &= ~AMCNTENCLR0_EL0_Pn_MASK; |
| 118 | value |= (px << AMCNTENCLR0_EL0_Pn_SHIFT) & AMCNTENCLR0_EL0_Pn_MASK; |
| 119 | |
| 120 | write_amcntenclr0_el0(value); |
| 121 | } |
| 122 | |
| 123 | static inline __unused void write_amcntenclr1_el0_px(uint64_t px) |
| 124 | { |
| 125 | uint64_t value = read_amcntenclr1_el0(); |
| 126 | |
| 127 | value &= ~AMCNTENCLR1_EL0_Pn_MASK; |
| 128 | value |= (px << AMCNTENCLR1_EL0_Pn_SHIFT) & AMCNTENCLR1_EL0_Pn_MASK; |
| 129 | |
| 130 | write_amcntenclr1_el0(value); |
| 131 | } |
| 132 | |
| 133 | static bool amu_supported(void) |
| 134 | { |
| 135 | return read_id_aa64pfr0_el1_amu() >= ID_AA64PFR0_AMU_V1; |
| 136 | } |
| 137 | |
| 138 | static bool amu_v1p1_supported(void) |
| 139 | { |
| 140 | return read_id_aa64pfr0_el1_amu() >= ID_AA64PFR0_AMU_V1P1; |
| 141 | } |
| 142 | |
| 143 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 144 | static bool amu_group1_supported(void) |
| 145 | { |
| 146 | return read_amcfgr_el0_ncg() > 0U; |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 147 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 148 | #endif |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 149 | |
| 150 | /* |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 151 | * Enable counters. This function is meant to be invoked |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 152 | * by the context management library before exiting from EL3. |
| 153 | */ |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 154 | void amu_enable(bool el2_unused, cpu_context_t *ctx) |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 155 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 156 | if (!amu_supported()) { |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 157 | return; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 158 | } |
| 159 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 160 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 161 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 162 | /* Check and set presence of group 1 counters */ |
| 163 | if (!amu_group1_supported()) { |
| 164 | ERROR("AMU Counter Group 1 is not implemented\n"); |
| 165 | panic(); |
| 166 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 167 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 168 | /* Check number of group 1 counters */ |
| 169 | uint64_t cnt_num = read_amcgcr_el0_cg1nc(); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 170 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 171 | VERBOSE("%s%llu. %s%u\n", |
| 172 | "Number of AMU Group 1 Counters ", cnt_num, |
| 173 | "Requested number ", AMU_GROUP1_NR_COUNTERS); |
| 174 | |
| 175 | if (cnt_num < AMU_GROUP1_NR_COUNTERS) { |
| 176 | ERROR("%s%llu is less than %s%u\n", |
| 177 | "Number of AMU Group 1 Counters ", cnt_num, |
| 178 | "Requested number ", AMU_GROUP1_NR_COUNTERS); |
| 179 | panic(); |
| 180 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 181 | } |
| 182 | #endif |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 183 | |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 184 | if (el2_unused) { |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 185 | /* |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 186 | * CPTR_EL2.TAM: Set to zero so any accesses to |
| 187 | * the Activity Monitor registers do not trap to EL2. |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 188 | */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 189 | write_cptr_el2_tam(0U); |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 190 | } |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 191 | |
| 192 | /* |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 193 | * Retrieve and update the CPTR_EL3 value from the context mentioned |
| 194 | * in 'ctx'. Set CPTR_EL3.TAM to zero so that any accesses to |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 195 | * the Activity Monitor registers do not trap to EL3. |
| 196 | */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 197 | write_cptr_el3_tam(ctx, 0U); |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 198 | |
| 199 | /* Enable group 0 counters */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 200 | write_amcntenset0_el0_px(AMU_GROUP0_COUNTERS_MASK); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 201 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 202 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 203 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 204 | /* Enable group 1 counters */ |
| 205 | write_amcntenset1_el0_px(AMU_GROUP1_COUNTERS_MASK); |
| 206 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 207 | #endif |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 208 | |
| 209 | /* Initialize FEAT_AMUv1p1 features if present. */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 210 | if (!amu_v1p1_supported()) { |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 211 | return; |
| 212 | } |
| 213 | |
| 214 | if (el2_unused) { |
| 215 | /* Make sure virtual offsets are disabled if EL2 not used. */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 216 | write_hcr_el2_amvoffen(0U); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | #if AMU_RESTRICT_COUNTERS |
| 220 | /* |
| 221 | * FEAT_AMUv1p1 adds a register field to restrict access to group 1 |
| 222 | * counters at all but the highest implemented EL. This is controlled |
| 223 | * with the AMU_RESTRICT_COUNTERS compile time flag, when set, system |
| 224 | * register reads at lower ELs return zero. Reads from the memory |
| 225 | * mapped view are unaffected. |
| 226 | */ |
| 227 | VERBOSE("AMU group 1 counter access restricted.\n"); |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 228 | write_amcr_el0_cg1rz(1U); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 229 | #else |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 230 | write_amcr_el0_cg1rz(0U); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 231 | #endif |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | /* Read the group 0 counter identified by the given `idx`. */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 235 | static uint64_t amu_group0_cnt_read(unsigned int idx) |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 236 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 237 | assert(amu_supported()); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 238 | assert(idx < AMU_GROUP0_NR_COUNTERS); |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 239 | |
| 240 | return amu_group0_cnt_read_internal(idx); |
| 241 | } |
| 242 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 243 | /* Write the group 0 counter identified by the given `idx` with `val` */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 244 | static void amu_group0_cnt_write(unsigned int idx, uint64_t val) |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 245 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 246 | assert(amu_supported()); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 247 | assert(idx < AMU_GROUP0_NR_COUNTERS); |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 248 | |
| 249 | amu_group0_cnt_write_internal(idx, val); |
| 250 | isb(); |
| 251 | } |
| 252 | |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 253 | /* |
| 254 | * Read the group 0 offset register for a given index. Index must be 0, 2, |
| 255 | * or 3, the register for 1 does not exist. |
| 256 | * |
| 257 | * Using this function requires FEAT_AMUv1p1 support. |
| 258 | */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 259 | static uint64_t amu_group0_voffset_read(unsigned int idx) |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 260 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 261 | assert(amu_v1p1_supported()); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 262 | assert(idx < AMU_GROUP0_NR_COUNTERS); |
| 263 | assert(idx != 1U); |
| 264 | |
| 265 | return amu_group0_voffset_read_internal(idx); |
| 266 | } |
| 267 | |
| 268 | /* |
| 269 | * Write the group 0 offset register for a given index. Index must be 0, 2, or |
| 270 | * 3, the register for 1 does not exist. |
| 271 | * |
| 272 | * Using this function requires FEAT_AMUv1p1 support. |
| 273 | */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 274 | static void amu_group0_voffset_write(unsigned int idx, uint64_t val) |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 275 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 276 | assert(amu_v1p1_supported()); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 277 | assert(idx < AMU_GROUP0_NR_COUNTERS); |
| 278 | assert(idx != 1U); |
| 279 | |
| 280 | amu_group0_voffset_write_internal(idx, val); |
| 281 | isb(); |
| 282 | } |
| 283 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 284 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 285 | /* Read the group 1 counter identified by the given `idx` */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 286 | static uint64_t amu_group1_cnt_read(unsigned int idx) |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 287 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 288 | assert(amu_supported()); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 289 | assert(amu_group1_supported()); |
| 290 | assert(idx < AMU_GROUP1_NR_COUNTERS); |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 291 | |
| 292 | return amu_group1_cnt_read_internal(idx); |
| 293 | } |
| 294 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 295 | /* Write the group 1 counter identified by the given `idx` with `val` */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 296 | static void amu_group1_cnt_write(unsigned int idx, uint64_t val) |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 297 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 298 | assert(amu_supported()); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 299 | assert(amu_group1_supported()); |
| 300 | assert(idx < AMU_GROUP1_NR_COUNTERS); |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 301 | |
| 302 | amu_group1_cnt_write_internal(idx, val); |
| 303 | isb(); |
| 304 | } |
| 305 | |
| 306 | /* |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 307 | * Read the group 1 offset register for a given index. |
| 308 | * |
| 309 | * Using this function requires FEAT_AMUv1p1 support. |
| 310 | */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 311 | static uint64_t amu_group1_voffset_read(unsigned int idx) |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 312 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 313 | assert(amu_v1p1_supported()); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 314 | assert(amu_group1_supported()); |
| 315 | assert(idx < AMU_GROUP1_NR_COUNTERS); |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 316 | assert((read_amcg1idr_el0_voff() & (UINT64_C(1) << idx)) != 0U); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 317 | |
| 318 | return amu_group1_voffset_read_internal(idx); |
| 319 | } |
| 320 | |
| 321 | /* |
| 322 | * Write the group 1 offset register for a given index. |
| 323 | * |
| 324 | * Using this function requires FEAT_AMUv1p1 support. |
| 325 | */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 326 | static void amu_group1_voffset_write(unsigned int idx, uint64_t val) |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 327 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 328 | assert(amu_v1p1_supported()); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 329 | assert(amu_group1_supported()); |
| 330 | assert(idx < AMU_GROUP1_NR_COUNTERS); |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 331 | assert((read_amcg1idr_el0_voff() & (UINT64_C(1) << idx)) != 0U); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 332 | |
| 333 | amu_group1_voffset_write_internal(idx, val); |
| 334 | isb(); |
| 335 | } |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 336 | #endif |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 337 | |
| 338 | static void *amu_context_save(const void *arg) |
| 339 | { |
| 340 | struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 341 | unsigned int i; |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 342 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 343 | if (!amu_supported()) { |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 344 | return (void *)-1; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 345 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 346 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 347 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 348 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 349 | if (!amu_group1_supported()) { |
| 350 | return (void *)-1; |
| 351 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 352 | } |
| 353 | #endif |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 354 | |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 355 | /* Assert that group 0/1 counter configuration is what we expect */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 356 | assert(read_amcntenset0_el0_px() == AMU_GROUP0_COUNTERS_MASK); |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 357 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 358 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 359 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 360 | assert(read_amcntenset1_el0_px() == AMU_GROUP1_COUNTERS_MASK); |
| 361 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 362 | #endif |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 363 | |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 364 | /* |
| 365 | * Disable group 0/1 counters to avoid other observers like SCP sampling |
| 366 | * counter values from the future via the memory mapped view. |
| 367 | */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 368 | write_amcntenclr0_el0_px(AMU_GROUP0_COUNTERS_MASK); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 369 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 370 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 371 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 372 | write_amcntenclr1_el0_px(AMU_GROUP1_COUNTERS_MASK); |
| 373 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 374 | #endif |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 375 | |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 376 | isb(); |
| 377 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 378 | /* Save all group 0 counters */ |
| 379 | for (i = 0U; i < AMU_GROUP0_NR_COUNTERS; i++) { |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 380 | ctx->group0_cnts[i] = amu_group0_cnt_read(i); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 381 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 382 | |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 383 | /* Save group 0 virtual offsets if supported and enabled. */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 384 | if (amu_v1p1_supported() && (read_hcr_el2_amvoffen() != 0U)) { |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 385 | /* Not using a loop because count is fixed and index 1 DNE. */ |
| 386 | ctx->group0_voffsets[0U] = amu_group0_voffset_read(0U); |
| 387 | ctx->group0_voffsets[1U] = amu_group0_voffset_read(2U); |
| 388 | ctx->group0_voffsets[2U] = amu_group0_voffset_read(3U); |
| 389 | } |
| 390 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 391 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 392 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 393 | /* Save group 1 counters */ |
| 394 | for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) { |
| 395 | if ((AMU_GROUP1_COUNTERS_MASK & (1UL << i)) != 0U) { |
| 396 | ctx->group1_cnts[i] = amu_group1_cnt_read(i); |
| 397 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 398 | } |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 399 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 400 | /* Save group 1 virtual offsets if supported and enabled. */ |
| 401 | if (amu_v1p1_supported() && (read_hcr_el2_amvoffen() != 0U)) { |
| 402 | uint64_t amcg1idr = read_amcg1idr_el0_voff() & |
| 403 | AMU_GROUP1_COUNTERS_MASK; |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 404 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 405 | for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) { |
| 406 | if (((amcg1idr >> i) & 1ULL) != 0ULL) { |
| 407 | ctx->group1_voffsets[i] = |
| 408 | amu_group1_voffset_read(i); |
| 409 | } |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 410 | } |
| 411 | } |
| 412 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 413 | #endif |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 414 | |
Antonio Nino Diaz | 033b4bb | 2018-10-25 16:52:26 +0100 | [diff] [blame] | 415 | return (void *)0; |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 416 | } |
| 417 | |
| 418 | static void *amu_context_restore(const void *arg) |
| 419 | { |
| 420 | struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 421 | unsigned int i; |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 422 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 423 | if (!amu_supported()) { |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 424 | return (void *)-1; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 425 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 426 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 427 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 428 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 429 | if (!amu_group1_supported()) { |
| 430 | return (void *)-1; |
| 431 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 432 | } |
| 433 | #endif |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 434 | |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 435 | /* Counters were disabled in `amu_context_save()` */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 436 | assert(read_amcntenset0_el0_px() == 0U); |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 437 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 438 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 439 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 440 | assert(read_amcntenset1_el0_px() == 0U); |
| 441 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 442 | #endif |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 443 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 444 | /* Restore all group 0 counters */ |
| 445 | for (i = 0U; i < AMU_GROUP0_NR_COUNTERS; i++) { |
| 446 | amu_group0_cnt_write(i, ctx->group0_cnts[i]); |
| 447 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 448 | |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 449 | /* Restore group 0 virtual offsets if supported and enabled. */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 450 | if (amu_v1p1_supported() && (read_hcr_el2_amvoffen() != 0U)) { |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 451 | /* Not using a loop because count is fixed and index 1 DNE. */ |
| 452 | amu_group0_voffset_write(0U, ctx->group0_voffsets[0U]); |
| 453 | amu_group0_voffset_write(2U, ctx->group0_voffsets[1U]); |
| 454 | amu_group0_voffset_write(3U, ctx->group0_voffsets[2U]); |
| 455 | } |
| 456 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 457 | /* Restore group 0 counter configuration */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 458 | write_amcntenset0_el0_px(AMU_GROUP0_COUNTERS_MASK); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 459 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 460 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 461 | if (AMU_GROUP1_NR_COUNTERS > 0U) { |
| 462 | /* Restore group 1 counters */ |
| 463 | for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) { |
| 464 | if ((AMU_GROUP1_COUNTERS_MASK & (1UL << i)) != 0U) { |
| 465 | amu_group1_cnt_write(i, ctx->group1_cnts[i]); |
| 466 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 467 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 468 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 469 | /* Restore group 1 virtual offsets if supported and enabled. */ |
| 470 | if (amu_v1p1_supported() && (read_hcr_el2_amvoffen() != 0U)) { |
| 471 | uint64_t amcg1idr = read_amcg1idr_el0_voff() & |
| 472 | AMU_GROUP1_COUNTERS_MASK; |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 473 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 474 | for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) { |
| 475 | if (((amcg1idr >> i) & 1ULL) != 0ULL) { |
| 476 | amu_group1_voffset_write(i, |
| 477 | ctx->group1_voffsets[i]); |
| 478 | } |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 479 | } |
| 480 | } |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 481 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame^] | 482 | /* Restore group 1 counter configuration */ |
| 483 | write_amcntenset1_el0_px(AMU_GROUP1_COUNTERS_MASK); |
| 484 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 485 | #endif |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 486 | |
Antonio Nino Diaz | 033b4bb | 2018-10-25 16:52:26 +0100 | [diff] [blame] | 487 | return (void *)0; |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 488 | } |
| 489 | |
| 490 | SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save); |
| 491 | SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, amu_context_restore); |