Nicolas Le Bayon | dc08ebe | 2019-09-11 11:46:40 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <errno.h> |
| 9 | #include <string.h> |
| 10 | |
| 11 | #include <common/bl_common.h> |
| 12 | #include <drivers/delay_timer.h> |
| 13 | #include <drivers/st/stm32_uart.h> |
| 14 | #include <drivers/st/stm32_uart_regs.h> |
| 15 | #include <drivers/st/stm32mp_clkfunc.h> |
| 16 | #include <lib/mmio.h> |
| 17 | |
| 18 | #include <platform_def.h> |
| 19 | |
| 20 | /* UART time-out value */ |
| 21 | #define STM32_UART_TIMEOUT_US 20000U |
| 22 | |
| 23 | /* Mask to clear ALL the configuration registers */ |
| 24 | |
| 25 | #define STM32_UART_CR1_FIELDS \ |
| 26 | (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ |
| 27 | USART_CR1_RE | USART_CR1_OVER8 | USART_CR1_FIFOEN) |
| 28 | |
| 29 | #define STM32_UART_CR2_FIELDS \ |
| 30 | (USART_CR2_SLVEN | USART_CR2_DIS_NSS | USART_CR2_ADDM7 | \ |
| 31 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ |
| 32 | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \ |
| 33 | USART_CR2_STOP | USART_CR2_LINEN | USART_CR2_SWAP | \ |
| 34 | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \ |
| 35 | USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMODE | \ |
| 36 | USART_CR2_RTOEN | USART_CR2_ADD) |
| 37 | |
| 38 | #define STM32_UART_CR3_FIELDS \ |
| 39 | (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | \ |
| 40 | USART_CR3_HDSEL | USART_CR3_NACK | USART_CR3_SCEN | \ |
| 41 | USART_CR3_DMAR | USART_CR3_DMAT | USART_CR3_RTSE | \ |
| 42 | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ |
| 43 | USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | \ |
| 44 | USART_CR3_DEP | USART_CR3_SCARCNT | USART_CR3_WUS | \ |
| 45 | USART_CR3_WUFIE | USART_CR3_TXFTIE | USART_CR3_TCBGTIE | \ |
| 46 | USART_CR3_RXFTCFG | USART_CR3_RXFTIE | USART_CR3_TXFTCFG) |
| 47 | |
| 48 | #define STM32_UART_ISR_ERRORS \ |
| 49 | (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE) |
| 50 | |
| 51 | static const uint16_t presc_table[STM32_UART_PRESCALER_NB] = { |
| 52 | 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U |
| 53 | }; |
| 54 | |
| 55 | /* @brief BRR division operation to set BRR register in 8-bit oversampling |
| 56 | * mode. |
| 57 | * @param clockfreq: UART clock. |
| 58 | * @param baud_rate: Baud rate set by the user. |
| 59 | * @param prescaler: UART prescaler value. |
| 60 | * @retval Division result. |
| 61 | */ |
| 62 | static uint32_t uart_div_sampling8(unsigned long clockfreq, |
| 63 | uint32_t baud_rate, |
| 64 | uint32_t prescaler) |
| 65 | { |
| 66 | uint32_t scaled_freq = clockfreq / presc_table[prescaler]; |
| 67 | |
| 68 | return ((scaled_freq * 2) + (baud_rate / 2)) / baud_rate; |
| 69 | |
| 70 | } |
| 71 | |
| 72 | /* @brief BRR division operation to set BRR register in 16-bit oversampling |
| 73 | * mode. |
| 74 | * @param clockfreq: UART clock. |
| 75 | * @param baud_rate: Baud rate set by the user. |
| 76 | * @param prescaler: UART prescaler value. |
| 77 | * @retval Division result. |
| 78 | */ |
| 79 | static uint32_t uart_div_sampling16(unsigned long clockfreq, |
| 80 | uint32_t baud_rate, |
| 81 | uint32_t prescaler) |
| 82 | { |
| 83 | uint32_t scaled_freq = clockfreq / presc_table[prescaler]; |
| 84 | |
| 85 | return (scaled_freq + (baud_rate / 2)) / baud_rate; |
| 86 | |
| 87 | } |
| 88 | |
| 89 | /* |
| 90 | * @brief Return the UART clock frequency. |
| 91 | * @param huart: UART handle. |
| 92 | * @retval Frequency value in Hz. |
| 93 | */ |
| 94 | static unsigned long uart_get_clock_freq(struct stm32_uart_handle_s *huart) |
| 95 | { |
| 96 | return fdt_get_uart_clock_freq((uintptr_t)huart->base); |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * @brief Configure the UART peripheral. |
| 101 | * @param huart: UART handle. |
| 102 | * @retval UART status. |
| 103 | */ |
| 104 | static int uart_set_config(struct stm32_uart_handle_s *huart, |
| 105 | const struct stm32_uart_init_s *init) |
| 106 | { |
| 107 | uint32_t tmpreg; |
| 108 | unsigned long clockfreq; |
| 109 | uint32_t brrtemp; |
| 110 | |
| 111 | /* |
| 112 | * ---------------------- USART CR1 Configuration -------------------- |
| 113 | * Clear M, PCE, PS, TE, RE and OVER8 bits and configure |
| 114 | * the UART word length, parity, mode and oversampling: |
| 115 | * - set the M bits according to init->word_length value, |
| 116 | * - set PCE and PS bits according to init->parity value, |
| 117 | * - set TE and RE bits according to init->mode value, |
| 118 | * - set OVER8 bit according to init->over_sampling value. |
| 119 | */ |
| 120 | tmpreg = init->word_length | |
| 121 | init->parity | |
| 122 | init->mode | |
| 123 | init->over_sampling | |
| 124 | init->fifo_mode; |
| 125 | mmio_clrsetbits_32(huart->base + USART_CR1, STM32_UART_CR1_FIELDS, tmpreg); |
| 126 | |
| 127 | /* |
| 128 | * --------------------- USART CR2 Configuration --------------------- |
| 129 | * Configure the UART Stop Bits: Set STOP[13:12] bits according |
| 130 | * to init->stop_bits value. |
| 131 | */ |
| 132 | mmio_clrsetbits_32(huart->base + USART_CR2, STM32_UART_CR2_FIELDS, |
| 133 | init->stop_bits); |
| 134 | |
| 135 | /* |
| 136 | * --------------------- USART CR3 Configuration --------------------- |
| 137 | * Configure: |
| 138 | * - UART HardWare Flow Control: set CTSE and RTSE bits according |
| 139 | * to init->hw_flow_control value, |
| 140 | * - one-bit sampling method versus three samples' majority rule |
| 141 | * according to init->one_bit_sampling (not applicable to |
| 142 | * LPUART), |
| 143 | * - set TXFTCFG bit according to init->tx_fifo_threshold value, |
| 144 | * - set RXFTCFG bit according to init->rx_fifo_threshold value. |
| 145 | */ |
| 146 | tmpreg = init->hw_flow_control | init->one_bit_sampling; |
| 147 | |
| 148 | if (init->fifo_mode == USART_CR1_FIFOEN) { |
| 149 | tmpreg |= init->tx_fifo_threshold | |
| 150 | init->rx_fifo_threshold; |
| 151 | } |
| 152 | |
| 153 | mmio_clrsetbits_32(huart->base + USART_CR3, STM32_UART_CR3_FIELDS, tmpreg); |
| 154 | |
| 155 | /* |
| 156 | * --------------------- USART PRESC Configuration ------------------- |
| 157 | * Configure UART Clock Prescaler : set PRESCALER according to |
| 158 | * init->prescaler value. |
| 159 | */ |
| 160 | assert(init->prescaler < STM32_UART_PRESCALER_NB); |
| 161 | mmio_clrsetbits_32(huart->base + USART_PRESC, USART_PRESC_PRESCALER, |
| 162 | init->prescaler); |
| 163 | |
| 164 | /*---------------------- USART BRR configuration --------------------*/ |
| 165 | clockfreq = uart_get_clock_freq(huart); |
| 166 | if (clockfreq == 0UL) { |
| 167 | return -ENODEV; |
| 168 | } |
| 169 | |
| 170 | if (init->over_sampling == STM32_UART_OVERSAMPLING_8) { |
| 171 | uint32_t usartdiv = uart_div_sampling8(clockfreq, |
| 172 | init->baud_rate, |
| 173 | init->prescaler); |
| 174 | |
| 175 | brrtemp = (usartdiv & USART_BRR_DIV_MANTISSA) | |
| 176 | ((usartdiv & USART_BRR_DIV_FRACTION) >> 1); |
| 177 | } else { |
| 178 | brrtemp = uart_div_sampling16(clockfreq, |
| 179 | init->baud_rate, |
| 180 | init->prescaler) & |
| 181 | (USART_BRR_DIV_FRACTION | USART_BRR_DIV_MANTISSA); |
| 182 | } |
| 183 | mmio_write_32(huart->base + USART_BRR, brrtemp); |
| 184 | |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | /* |
| 189 | * @brief Handle UART communication timeout. |
| 190 | * @param huart: UART handle. |
| 191 | * @param flag: Specifies the UART flag to check. |
| 192 | * @retval UART status. |
| 193 | */ |
| 194 | static int stm32_uart_wait_flag(struct stm32_uart_handle_s *huart, uint32_t flag) |
| 195 | { |
| 196 | uint64_t timeout_ref = timeout_init_us(STM32_UART_TIMEOUT_US); |
| 197 | |
| 198 | while ((mmio_read_32(huart->base + USART_ISR) & flag) == 0U) { |
| 199 | if (timeout_elapsed(timeout_ref)) { |
| 200 | return -ETIMEDOUT; |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | return 0; |
| 205 | } |
| 206 | |
| 207 | /* |
| 208 | * @brief Check the UART idle State. |
| 209 | * @param huart: UART handle. |
| 210 | * @retval UART status. |
| 211 | */ |
| 212 | static int stm32_uart_check_idle(struct stm32_uart_handle_s *huart) |
| 213 | { |
| 214 | int ret; |
| 215 | |
| 216 | /* Check if the transmitter is enabled */ |
| 217 | if ((mmio_read_32(huart->base + USART_CR1) & USART_CR1_TE) == USART_CR1_TE) { |
| 218 | ret = stm32_uart_wait_flag(huart, USART_ISR_TEACK); |
| 219 | if (ret != 0) { |
| 220 | return ret; |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | /* Check if the receiver is enabled */ |
| 225 | if ((mmio_read_32(huart->base + USART_CR1) & USART_CR1_RE) == USART_CR1_RE) { |
| 226 | ret = stm32_uart_wait_flag(huart, USART_ISR_REACK); |
| 227 | if (ret != 0) { |
| 228 | return ret; |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | return 0; |
| 233 | } |
| 234 | |
| 235 | /* |
| 236 | * @brief Compute RDR register mask depending on word length. |
| 237 | * @param huart: UART handle. |
| 238 | * @retval Mask value. |
| 239 | */ |
| 240 | static unsigned int stm32_uart_rdr_mask(const struct stm32_uart_init_s *init) |
| 241 | { |
| 242 | unsigned int mask = 0U; |
| 243 | |
| 244 | switch (init->word_length) { |
| 245 | case STM32_UART_WORDLENGTH_9B: |
| 246 | mask = GENMASK(8, 0); |
| 247 | break; |
| 248 | case STM32_UART_WORDLENGTH_8B: |
| 249 | mask = GENMASK(7, 0); |
| 250 | break; |
| 251 | case STM32_UART_WORDLENGTH_7B: |
| 252 | mask = GENMASK(6, 0); |
| 253 | break; |
| 254 | default: |
| 255 | break; /* not reached */ |
| 256 | } |
| 257 | |
| 258 | if (init->parity != STM32_UART_PARITY_NONE) { |
| 259 | mask >>= 1; |
| 260 | } |
| 261 | |
| 262 | return mask; |
| 263 | } |
| 264 | |
| 265 | /* |
| 266 | * @brief Check interrupt and status errors. |
| 267 | * @retval True if error detected, false otherwise. |
| 268 | */ |
| 269 | static bool stm32_uart_error_detected(struct stm32_uart_handle_s *huart) |
| 270 | { |
| 271 | return (mmio_read_32(huart->base + USART_ISR) & STM32_UART_ISR_ERRORS) != 0U; |
| 272 | } |
| 273 | |
| 274 | /* |
| 275 | * @brief Clear status errors. |
| 276 | */ |
| 277 | static void stm32_uart_error_clear(struct stm32_uart_handle_s *huart) |
| 278 | { |
| 279 | mmio_write_32(huart->base + USART_ICR, STM32_UART_ISR_ERRORS); |
| 280 | } |
| 281 | |
| 282 | /* |
| 283 | * @brief Stop the UART. |
| 284 | * @param base: UART base address. |
| 285 | */ |
| 286 | void stm32_uart_stop(uintptr_t base) |
| 287 | { |
| 288 | mmio_clrbits_32(base + USART_CR1, USART_CR1_UE); |
| 289 | } |
| 290 | |
| 291 | /* |
| 292 | * @brief Initialize UART. |
| 293 | * @param huart: UART handle. |
| 294 | * @param base_addr: base address of UART. |
| 295 | * @param init: UART initialization parameter. |
| 296 | * @retval UART status. |
| 297 | */ |
| 298 | |
| 299 | int stm32_uart_init(struct stm32_uart_handle_s *huart, |
| 300 | uintptr_t base_addr, |
| 301 | const struct stm32_uart_init_s *init) |
| 302 | { |
| 303 | int ret; |
| 304 | |
| 305 | if (huart == NULL || init == NULL || base_addr == 0U) { |
| 306 | return -EINVAL; |
| 307 | } |
| 308 | |
| 309 | huart->base = base_addr; |
| 310 | |
| 311 | /* Disable the peripheral */ |
| 312 | stm32_uart_stop(huart->base); |
| 313 | |
| 314 | /* Computation of UART mask to apply to RDR register */ |
| 315 | huart->rdr_mask = stm32_uart_rdr_mask(init); |
| 316 | |
| 317 | /* Init the peripheral */ |
| 318 | ret = uart_set_config(huart, init); |
| 319 | if (ret != 0) { |
| 320 | return ret; |
| 321 | } |
| 322 | |
| 323 | /* Enable the peripheral */ |
| 324 | mmio_setbits_32(huart->base + USART_CR1, USART_CR1_UE); |
| 325 | |
| 326 | /* TEACK and/or REACK to check */ |
| 327 | return stm32_uart_check_idle(huart); |
| 328 | } |
| 329 | |
| 330 | /* |
| 331 | * @brief Transmit one data in no blocking mode. |
| 332 | * @param huart: UART handle. |
| 333 | * @param c: data to sent. |
| 334 | * @retval UART status. |
| 335 | */ |
| 336 | int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c) |
| 337 | { |
| 338 | int ret; |
| 339 | |
| 340 | if (huart == NULL) { |
| 341 | return -EINVAL; |
| 342 | } |
| 343 | |
| 344 | ret = stm32_uart_wait_flag(huart, USART_ISR_TXE); |
| 345 | if (ret != 0) { |
| 346 | return ret; |
| 347 | } |
| 348 | |
| 349 | mmio_write_32(huart->base + USART_TDR, c); |
| 350 | if (stm32_uart_error_detected(huart)) { |
| 351 | stm32_uart_error_clear(huart); |
| 352 | return -EFAULT; |
| 353 | } |
| 354 | |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | /* |
| 359 | * @brief Flush TX Transmit fifo |
| 360 | * @param huart: UART handle. |
| 361 | * @retval UART status. |
| 362 | */ |
| 363 | int stm32_uart_flush(struct stm32_uart_handle_s *huart) |
| 364 | { |
| 365 | int ret; |
| 366 | |
| 367 | if (huart == NULL) { |
| 368 | return -EINVAL; |
| 369 | } |
| 370 | |
| 371 | ret = stm32_uart_wait_flag(huart, USART_ISR_TXE); |
| 372 | if (ret != 0) { |
| 373 | return ret; |
| 374 | } |
| 375 | |
| 376 | return stm32_uart_wait_flag(huart, USART_ISR_TC); |
| 377 | } |
| 378 | |
| 379 | /* |
| 380 | * @brief Receive a data in no blocking mode. |
| 381 | * @retval value if >0 or UART status. |
| 382 | */ |
| 383 | int stm32_uart_getc(struct stm32_uart_handle_s *huart) |
| 384 | { |
| 385 | uint32_t data; |
| 386 | |
| 387 | if (huart == NULL) { |
| 388 | return -EINVAL; |
| 389 | } |
| 390 | |
| 391 | /* Check if data is available */ |
| 392 | if ((mmio_read_32(huart->base + USART_ISR) & USART_ISR_RXNE) == 0U) { |
| 393 | return -EAGAIN; |
| 394 | } |
| 395 | |
| 396 | data = mmio_read_32(huart->base + USART_RDR) & huart->rdr_mask; |
| 397 | |
| 398 | if (stm32_uart_error_detected(huart)) { |
| 399 | stm32_uart_error_clear(huart); |
| 400 | return -EFAULT; |
| 401 | } |
| 402 | |
| 403 | return (int)data; |
| 404 | } |