blob: 22a7f2b83bc1e2253a904a7672897183955b7a7f [file] [log] [blame]
Anson Huangf753d462019-01-15 10:34:04 +08001/*
2 * Copyright 2019 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdlib.h>
8#include <stdint.h>
9#include <std_svc.h>
10#include <platform_def.h>
11#include <common/debug.h>
12#include <common/runtime_svc.h>
13#include <imx_sip_svc.h>
14#include <sci/sci.h>
15
Anson Huang922c45f2019-01-15 10:56:36 +080016#ifdef PLAT_IMX8QM
17const static int ap_cluster_index[PLATFORM_CLUSTER_COUNT] = {
18 SC_R_A53, SC_R_A72,
19};
20#endif
21
Anson Huangf753d462019-01-15 10:34:04 +080022static int imx_srtc_set_time(uint32_t year_mon,
23 unsigned long day_hour,
24 unsigned long min_sec)
25{
26 return sc_timer_set_rtc_time(ipc_handle,
27 year_mon >> 16, year_mon & 0xffff,
28 day_hour >> 16, day_hour & 0xffff,
29 min_sec >> 16, min_sec & 0xffff);
30}
31
32int imx_srtc_handler(uint32_t smc_fid,
33 void *handle,
34 u_register_t x1,
35 u_register_t x2,
36 u_register_t x3,
37 u_register_t x4)
38{
39 int ret;
40
41 switch (x1) {
42 case IMX_SIP_SRTC_SET_TIME:
43 ret = imx_srtc_set_time(x2, x3, x4);
44 break;
45 default:
46 ret = SMC_UNK;
47 }
48
49 SMC_RET1(handle, ret);
50}
Anson Huang922c45f2019-01-15 10:56:36 +080051
52static void imx_cpufreq_set_target(uint32_t cluster_id, unsigned long freq)
53{
54 sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq;
55
56#ifdef PLAT_IMX8QM
57 sc_pm_set_clock_rate(ipc_handle, ap_cluster_index[cluster_id], SC_PM_CLK_CPU, &rate);
58#endif
59#ifdef PLAT_IMX8QX
60 sc_pm_set_clock_rate(ipc_handle, SC_R_A35, SC_PM_CLK_CPU, &rate);
61#endif
62}
63
64int imx_cpufreq_handler(uint32_t smc_fid,
65 u_register_t x1,
66 u_register_t x2,
67 u_register_t x3)
68{
69 switch (x1) {
70 case IMX_SIP_SET_CPUFREQ:
71 imx_cpufreq_set_target(x2, x3);
72 break;
73 default:
74 return SMC_UNK;
75 }
76
77 return 0;
78}