blob: 283b6064124802db3f8dcfb3ce4e7335d495cb95 [file] [log] [blame]
XiaoDong Huang83f79a82019-06-13 10:55:50 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PX30_DEF_H__
8#define __PX30_DEF_H__
9
10#define MAJOR_VERSION (1)
11#define MINOR_VERSION (0)
12
13#define SIZE_K(n) ((n) * 1024)
14
15#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
16
17/* Special value used to verify platform parameters from BL2 to BL3-1 */
18#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
19
20#define PMU_BASE 0xff000000
21#define PMU_SIZE SIZE_K(64)
22
23#define PMUGRF_BASE 0xff010000
24#define PMUGRF_SIZE SIZE_K(64)
25
26#define PMUSRAM_BASE 0xff020000
27#define PMUSRAM_SIZE SIZE_K(64)
28#define PMUSRAM_RSIZE SIZE_K(8)
29
30#define UART0_BASE 0xff030000
31#define UART0_SIZE SIZE_K(64)
32
33#define GPIO0_BASE 0xff040000
34#define GPIO0_SIZE SIZE_K(64)
35
36#define PMUSGRF_BASE 0xff050000
37#define PMUSGRF_SIZE SIZE_K(64)
38
39#define INTSRAM_BASE 0xff0e0000
40#define INTSRAM_SIZE SIZE_K(64)
41
42#define SGRF_BASE 0xff11c000
43#define SGRF_SIZE SIZE_K(16)
44
45#define GIC400_BASE 0xff130000
46#define GIC400_SIZE SIZE_K(64)
47
48#define GRF_BASE 0xff140000
49#define GRF_SIZE SIZE_K(64)
50
51#define UART1_BASE 0xff158000
52#define UART1_SIZE SIZE_K(64)
53
54#define UART2_BASE 0xff160000
55#define UART2_SIZE SIZE_K(64)
56
Paul Kocialkowski91e299c2019-11-27 14:59:36 +010057#define UART3_BASE 0xff168000
58#define UART3_SIZE SIZE_K(64)
59
Heiko Stuebner64a4a7a2019-08-05 09:45:09 +020060#define UART5_BASE 0xff178000
61#define UART5_SIZE SIZE_K(64)
62
XiaoDong Huang83f79a82019-06-13 10:55:50 +080063#define I2C0_BASE 0xff180000
64#define I2C0_SIZE SIZE_K(64)
65
66#define PWM0_BASE 0xff200000
67#define PWM0_SIZE SIZE_K(32)
68
69#define PWM1_BASE 0xff208000
70#define PWM1_SIZE SIZE_K(32)
71
72#define NTIME_BASE 0xff210000
73#define NTIME_SIZE SIZE_K(64)
74
75#define STIME_BASE 0xff220000
76#define STIME_SIZE SIZE_K(64)
77
78#define DCF_BASE 0xff230000
79#define DCF_SIZE SIZE_K(64)
80
81#define GPIO1_BASE 0xff250000
82#define GPIO1_SIZE SIZE_K(64)
83
84#define GPIO2_BASE 0xff260000
85#define GPIO2_SIZE SIZE_K(64)
86
87#define GPIO3_BASE 0xff270000
88#define GPIO3_SIZE SIZE_K(64)
89
90#define DDR_PHY_BASE 0xff2a0000
91#define DDR_PHY_SIZE SIZE_K(64)
92
93#define CRU_BASE 0xff2b0000
94#define CRU_SIZE SIZE_K(32)
95
96#define CRU_BOOST_BASE 0xff2b8000
97#define CRU_BOOST_SIZE SIZE_K(16)
98
99#define PMUCRU_BASE 0xff2bc000
100#define PMUCRU_SIZE SIZE_K(16)
101
102#define VOP_BASE 0xff460000
103#define VOP_SIZE SIZE_K(16)
104
105#define SERVER_MSCH_BASE 0xff530000
106#define SERVER_MSCH_SIZE SIZE_K(64)
107
108#define FIREWALL_DDR_BASE 0xff534000
109#define FIREWALL_DDR_SIZE SIZE_K(16)
110
111#define DDR_UPCTL_BASE 0xff600000
112#define DDR_UPCTL_SIZE SIZE_K(64)
113
114#define DDR_MNTR_BASE 0xff610000
115#define DDR_MNTR_SIZE SIZE_K(64)
116
117#define DDR_STDBY_BASE 0xff620000
118#define DDR_STDBY_SIZE SIZE_K(64)
119
120#define DDRGRF_BASE 0xff630000
121#define DDRGRF_SIZE SIZE_K(32)
122
123/**************************************************************************
124 * UART related constants
125 **************************************************************************/
126#define PX30_UART_BASE UART2_BASE
127#define PX30_BAUDRATE 1500000
128#define PX30_UART_CLOCK 24000000
129
130/******************************************************************************
131 * System counter frequency related constants
132 ******************************************************************************/
133#define SYS_COUNTER_FREQ_IN_TICKS 24000000
134#define SYS_COUNTER_FREQ_IN_MHZ 24
135
136/******************************************************************************
137 * GIC-400 & interrupt handling related constants
138 ******************************************************************************/
139
140/* Base rk_platform compatible GIC memory map */
141#define PX30_GICD_BASE (GIC400_BASE + 0x1000)
142#define PX30_GICC_BASE (GIC400_BASE + 0x2000)
143#define PX30_GICR_BASE 0 /* no GICR in GIC-400 */
144
145/******************************************************************************
146 * sgi, ppi
147 ******************************************************************************/
148#define RK_IRQ_SEC_PHY_TIMER 29
149
150#define RK_IRQ_SEC_SGI_0 8
151#define RK_IRQ_SEC_SGI_1 9
152#define RK_IRQ_SEC_SGI_2 10
153#define RK_IRQ_SEC_SGI_3 11
154#define RK_IRQ_SEC_SGI_4 12
155#define RK_IRQ_SEC_SGI_5 13
156#define RK_IRQ_SEC_SGI_6 14
157#define RK_IRQ_SEC_SGI_7 15
158
159/*
160 * Define a list of Group 0 interrupts.
161 */
162#define PLAT_RK_GICV2_G0_IRQS \
163 INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
164 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
165 INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
166 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
167
168#define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/
169#define SHARE_MEM_PAGE_NUM 15
170#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4)
171
172#define DDR_PARAM_BASE 0x02000000
173#define DDR_PARAM_SIZE SIZE_K(4)
174
175#endif /* __PLAT_DEF_H__ */