Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Manish V Badarkhe | 7672edf | 2020-08-03 18:43:14 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 7 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <common/bl_common.h> |
| 9 | #include <common/debug.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 10 | #include <cortex_a53.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Boyan Karatotev | 5d38cb3 | 2023-01-27 09:37:07 +0000 | [diff] [blame] | 13 | #include <lib/cpus/errata.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 15 | #if A53_DISABLE_NON_TEMPORAL_HINT |
| 16 | #undef ERRATA_A53_836870 |
| 17 | #define ERRATA_A53_836870 1 |
| 18 | #endif |
| 19 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 20 | /* --------------------------------------------- |
| 21 | * Disable L1 data cache and unified L2 cache |
| 22 | * --------------------------------------------- |
| 23 | */ |
| 24 | func cortex_a53_disable_dcache |
| 25 | mrs x1, sctlr_el3 |
| 26 | bic x1, x1, #SCTLR_C_BIT |
| 27 | msr sctlr_el3, x1 |
| 28 | isb |
| 29 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 30 | endfunc cortex_a53_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 31 | |
| 32 | /* --------------------------------------------- |
| 33 | * Disable intra-cluster coherency |
| 34 | * --------------------------------------------- |
| 35 | */ |
| 36 | func cortex_a53_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 37 | mrs x0, CORTEX_A53_ECTLR_EL1 |
| 38 | bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT |
| 39 | msr CORTEX_A53_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 40 | isb |
| 41 | dsb sy |
| 42 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 43 | endfunc cortex_a53_disable_smp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 44 | |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 45 | /* --------------------------------------------------- |
| 46 | * Errata Workaround for Cortex A53 Errata #819472. |
| 47 | * This applies only to revision <= r0p1 of Cortex A53. |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 48 | * Due to the nature of the errata it is applied unconditionally |
| 49 | * when built in, report it as applicable in this case |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 50 | * --------------------------------------------------- |
| 51 | */ |
| 52 | func check_errata_819472 |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 53 | #if ERRATA_A53_819472 |
| 54 | mov x0, #ERRATA_APPLIES |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 55 | ret |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 56 | #else |
| 57 | mov x1, #0x01 |
| 58 | b cpu_rev_var_ls |
| 59 | #endif |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 60 | endfunc check_errata_819472 |
| 61 | |
| 62 | /* --------------------------------------------------- |
| 63 | * Errata Workaround for Cortex A53 Errata #824069. |
| 64 | * This applies only to revision <= r0p2 of Cortex A53. |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 65 | * Due to the nature of the errata it is applied unconditionally |
| 66 | * when built in, report it as applicable in this case |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 67 | * --------------------------------------------------- |
| 68 | */ |
| 69 | func check_errata_824069 |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 70 | #if ERRATA_A53_824069 |
| 71 | mov x0, #ERRATA_APPLIES |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 72 | ret |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 73 | #else |
| 74 | mov x1, #0x02 |
| 75 | b cpu_rev_var_ls |
| 76 | #endif |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 77 | endfunc check_errata_824069 |
| 78 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 79 | /* -------------------------------------------------- |
| 80 | * Errata Workaround for Cortex A53 Errata #826319. |
| 81 | * This applies only to revision <= r0p2 of Cortex A53. |
| 82 | * Inputs: |
| 83 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 84 | * Shall clobber: x0-x17 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 85 | * -------------------------------------------------- |
| 86 | */ |
| 87 | func errata_a53_826319_wa |
| 88 | /* |
| 89 | * Compare x0 against revision r0p2 |
| 90 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 91 | mov x17, x30 |
| 92 | bl check_errata_826319 |
| 93 | cbz x0, 1f |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 94 | mrs x1, CORTEX_A53_L2ACTLR_EL1 |
| 95 | bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN |
| 96 | orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH |
| 97 | msr CORTEX_A53_L2ACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 98 | 1: |
| 99 | ret x17 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 100 | endfunc errata_a53_826319_wa |
| 101 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 102 | func check_errata_826319 |
| 103 | mov x1, #0x02 |
| 104 | b cpu_rev_var_ls |
| 105 | endfunc check_errata_826319 |
| 106 | |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 107 | /* --------------------------------------------------- |
| 108 | * Errata Workaround for Cortex A53 Errata #827319. |
| 109 | * This applies only to revision <= r0p2 of Cortex A53. |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 110 | * Due to the nature of the errata it is applied unconditionally |
| 111 | * when built in, report it as applicable in this case |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 112 | * --------------------------------------------------- |
| 113 | */ |
| 114 | func check_errata_827319 |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 115 | #if ERRATA_A53_827319 |
| 116 | mov x0, #ERRATA_APPLIES |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 117 | ret |
Andrew F. Davis | 3e2ef2e | 2019-04-24 16:11:03 -0400 | [diff] [blame] | 118 | #else |
| 119 | mov x1, #0x02 |
| 120 | b cpu_rev_var_ls |
| 121 | #endif |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 122 | endfunc check_errata_827319 |
| 123 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 124 | /* --------------------------------------------------------------------- |
| 125 | * Disable the cache non-temporal hint. |
| 126 | * |
| 127 | * This ignores the Transient allocation hint in the MAIR and treats |
| 128 | * allocations the same as non-transient allocation types. As a result, |
| 129 | * the LDNP and STNP instructions in AArch64 behave the same as the |
| 130 | * equivalent LDP and STP instructions. |
| 131 | * |
| 132 | * This is relevant only for revisions <= r0p3 of Cortex-A53. |
| 133 | * From r0p4 and onwards, the bit to disable the hint is enabled by |
| 134 | * default at reset. |
| 135 | * |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 136 | * Inputs: |
| 137 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 138 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 139 | * --------------------------------------------------------------------- |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 140 | */ |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 141 | func a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 142 | /* |
| 143 | * Compare x0 against revision r0p3 |
| 144 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 145 | mov x17, x30 |
| 146 | bl check_errata_disable_non_temporal_hint |
| 147 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 148 | mrs x1, CORTEX_A53_CPUACTLR_EL1 |
| 149 | orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH |
| 150 | msr CORTEX_A53_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 151 | 1: |
| 152 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 153 | endfunc a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 154 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 155 | func check_errata_disable_non_temporal_hint |
| 156 | mov x1, #0x03 |
| 157 | b cpu_rev_var_ls |
| 158 | endfunc check_errata_disable_non_temporal_hint |
| 159 | |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 160 | /* -------------------------------------------------- |
| 161 | * Errata Workaround for Cortex A53 Errata #855873. |
| 162 | * |
| 163 | * This applies only to revisions >= r0p3 of Cortex A53. |
| 164 | * Earlier revisions of the core are affected as well, but don't |
| 165 | * have the chicken bit in the CPUACTLR register. It is expected that |
| 166 | * the rich OS takes care of that, especially as the workaround is |
| 167 | * shared with other erratas in those revisions of the CPU. |
| 168 | * Inputs: |
| 169 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 170 | * Shall clobber: x0-x17 |
| 171 | * -------------------------------------------------- |
| 172 | */ |
| 173 | func errata_a53_855873_wa |
| 174 | /* |
| 175 | * Compare x0 against revision r0p3 and higher |
| 176 | */ |
| 177 | mov x17, x30 |
| 178 | bl check_errata_855873 |
| 179 | cbz x0, 1f |
| 180 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 181 | mrs x1, CORTEX_A53_CPUACTLR_EL1 |
| 182 | orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI |
| 183 | msr CORTEX_A53_CPUACTLR_EL1, x1 |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 184 | 1: |
| 185 | ret x17 |
| 186 | endfunc errata_a53_855873_wa |
| 187 | |
| 188 | func check_errata_855873 |
| 189 | mov x1, #0x03 |
| 190 | b cpu_rev_var_hs |
| 191 | endfunc check_errata_855873 |
| 192 | |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 193 | /* |
| 194 | * Errata workaround for Cortex A53 Errata #835769. |
| 195 | * This applies to revisions <= r0p4 of Cortex A53. |
| 196 | * This workaround is statically enabled at build time. |
| 197 | */ |
| 198 | func check_errata_835769 |
Jonathan Wright | 6e1796e | 2018-03-28 16:55:54 +0100 | [diff] [blame] | 199 | cmp x0, #0x04 |
| 200 | b.hi errata_not_applies |
| 201 | /* |
| 202 | * Fix potentially available for revisions r0p2, r0p3 and r0p4. |
| 203 | * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. |
| 204 | */ |
| 205 | cmp x0, #0x01 |
| 206 | mov x0, #ERRATA_APPLIES |
| 207 | b.ls exit_check_errata_835769 |
| 208 | /* Load REVIDR. */ |
| 209 | mrs x1, revidr_el1 |
| 210 | /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ |
| 211 | tbz x1, #7, exit_check_errata_835769 |
| 212 | errata_not_applies: |
| 213 | mov x0, #ERRATA_NOT_APPLIES |
| 214 | exit_check_errata_835769: |
| 215 | ret |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 216 | endfunc check_errata_835769 |
| 217 | |
| 218 | /* |
| 219 | * Errata workaround for Cortex A53 Errata #843419. |
| 220 | * This applies to revisions <= r0p4 of Cortex A53. |
| 221 | * This workaround is statically enabled at build time. |
| 222 | */ |
| 223 | func check_errata_843419 |
Jonathan Wright | efb1f33 | 2018-03-28 15:52:03 +0100 | [diff] [blame] | 224 | mov x1, #ERRATA_APPLIES |
| 225 | mov x2, #ERRATA_NOT_APPLIES |
| 226 | cmp x0, #0x04 |
| 227 | csel x0, x1, x2, ls |
| 228 | /* |
| 229 | * Fix potentially available for revision r0p4. |
| 230 | * If r0p4 check for fix in REVIDR, else exit. |
| 231 | */ |
| 232 | b.ne exit_check_errata_843419 |
| 233 | /* Load REVIDR. */ |
| 234 | mrs x3, revidr_el1 |
| 235 | /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ |
| 236 | tbz x3, #8, exit_check_errata_843419 |
| 237 | mov x0, x2 |
| 238 | exit_check_errata_843419: |
| 239 | ret |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 240 | endfunc check_errata_843419 |
| 241 | |
Manish V Badarkhe | 7672edf | 2020-08-03 18:43:14 +0100 | [diff] [blame] | 242 | /* -------------------------------------------------- |
| 243 | * Errata workaround for Cortex A53 Errata #1530924. |
| 244 | * This applies to all revisions of Cortex A53. |
| 245 | * -------------------------------------------------- |
| 246 | */ |
| 247 | func check_errata_1530924 |
| 248 | #if ERRATA_A53_1530924 |
| 249 | mov x0, #ERRATA_APPLIES |
| 250 | #else |
| 251 | mov x0, #ERRATA_MISSING |
| 252 | #endif |
| 253 | ret |
| 254 | endfunc check_errata_1530924 |
| 255 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 256 | /* ------------------------------------------------- |
| 257 | * The CPU Ops reset function for Cortex-A53. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 258 | * Shall clobber: x0-x19 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 259 | * ------------------------------------------------- |
| 260 | */ |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 261 | func cortex_a53_reset_func |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 262 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 263 | bl cpu_get_rev_var |
| 264 | mov x18, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 265 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 266 | |
| 267 | #if ERRATA_A53_826319 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 268 | mov x0, x18 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 269 | bl errata_a53_826319_wa |
| 270 | #endif |
| 271 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 272 | #if ERRATA_A53_836870 |
| 273 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 274 | bl a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 275 | #endif |
| 276 | |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 277 | #if ERRATA_A53_855873 |
| 278 | mov x0, x18 |
| 279 | bl errata_a53_855873_wa |
| 280 | #endif |
| 281 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 282 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 283 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 284 | * --------------------------------------------- |
| 285 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 286 | mrs x0, CORTEX_A53_ECTLR_EL1 |
| 287 | orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT |
| 288 | msr CORTEX_A53_ECTLR_EL1, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 289 | isb |
| 290 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 291 | endfunc cortex_a53_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 292 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 293 | func cortex_a53_core_pwr_dwn |
| 294 | mov x18, x30 |
| 295 | |
| 296 | /* --------------------------------------------- |
| 297 | * Turn off caches. |
| 298 | * --------------------------------------------- |
| 299 | */ |
| 300 | bl cortex_a53_disable_dcache |
| 301 | |
| 302 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 303 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 304 | * --------------------------------------------- |
| 305 | */ |
| 306 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 307 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 308 | |
| 309 | /* --------------------------------------------- |
| 310 | * Come out of intra cluster coherency |
| 311 | * --------------------------------------------- |
| 312 | */ |
| 313 | mov x30, x18 |
| 314 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 315 | endfunc cortex_a53_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 316 | |
| 317 | func cortex_a53_cluster_pwr_dwn |
| 318 | mov x18, x30 |
| 319 | |
| 320 | /* --------------------------------------------- |
| 321 | * Turn off caches. |
| 322 | * --------------------------------------------- |
| 323 | */ |
| 324 | bl cortex_a53_disable_dcache |
| 325 | |
| 326 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 327 | * Flush L1 caches. |
| 328 | * --------------------------------------------- |
| 329 | */ |
| 330 | mov x0, #DCCISW |
| 331 | bl dcsw_op_level1 |
| 332 | |
| 333 | /* --------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 334 | * Disable the optional ACP. |
| 335 | * --------------------------------------------- |
| 336 | */ |
| 337 | bl plat_disable_acp |
| 338 | |
| 339 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 340 | * Flush L2 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 341 | * --------------------------------------------- |
| 342 | */ |
| 343 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 344 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 345 | |
| 346 | /* --------------------------------------------- |
| 347 | * Come out of intra cluster coherency |
| 348 | * --------------------------------------------- |
| 349 | */ |
| 350 | mov x30, x18 |
| 351 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 352 | endfunc cortex_a53_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 353 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 354 | #if REPORT_ERRATA |
| 355 | /* |
| 356 | * Errata printing function for Cortex A53. Must follow AAPCS. |
| 357 | */ |
| 358 | func cortex_a53_errata_report |
| 359 | stp x8, x30, [sp, #-16]! |
| 360 | |
| 361 | bl cpu_get_rev_var |
| 362 | mov x8, x0 |
| 363 | |
| 364 | /* |
| 365 | * Report all errata. The revision-variant information is passed to |
| 366 | * checking functions of each errata. |
| 367 | */ |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 368 | report_errata ERRATA_A53_819472, cortex_a53, 819472 |
| 369 | report_errata ERRATA_A53_824069, cortex_a53, 824069 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 370 | report_errata ERRATA_A53_826319, cortex_a53, 826319 |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 371 | report_errata ERRATA_A53_827319, cortex_a53, 827319 |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 372 | report_errata ERRATA_A53_835769, cortex_a53, 835769 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 373 | report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 374 | report_errata ERRATA_A53_843419, cortex_a53, 843419 |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 375 | report_errata ERRATA_A53_855873, cortex_a53, 855873 |
Manish V Badarkhe | 7672edf | 2020-08-03 18:43:14 +0100 | [diff] [blame] | 376 | report_errata ERRATA_A53_1530924, cortex_a53, 1530924 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 377 | |
| 378 | ldp x8, x30, [sp], #16 |
| 379 | ret |
| 380 | endfunc cortex_a53_errata_report |
| 381 | #endif |
| 382 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 383 | /* --------------------------------------------- |
| 384 | * This function provides cortex_a53 specific |
| 385 | * register information for crash reporting. |
| 386 | * It needs to return with x6 pointing to |
| 387 | * a list of register names in ascii and |
| 388 | * x8 - x15 having values of registers to be |
| 389 | * reported. |
| 390 | * --------------------------------------------- |
| 391 | */ |
| 392 | .section .rodata.cortex_a53_regs, "aS" |
| 393 | cortex_a53_regs: /* The ascii list of register names to be reported */ |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 394 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ |
| 395 | "cpuactlr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 396 | |
| 397 | func cortex_a53_cpu_reg_dump |
| 398 | adr x6, cortex_a53_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 399 | mrs x8, CORTEX_A53_ECTLR_EL1 |
| 400 | mrs x9, CORTEX_A53_MERRSR_EL1 |
| 401 | mrs x10, CORTEX_A53_L2MERRSR_EL1 |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 402 | mrs x11, CORTEX_A53_CPUACTLR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 403 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 404 | endfunc cortex_a53_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 405 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 406 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 407 | cortex_a53_reset_func, \ |
| 408 | cortex_a53_core_pwr_dwn, \ |
| 409 | cortex_a53_cluster_pwr_dwn |