Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 1 | /* |
Sona Mathew | d7c07d1 | 2023-06-25 19:25:20 -0500 | [diff] [blame] | 2 | * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. |
Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
| 10 | #include <cortex_a15.h> |
| 11 | #include <cpu_macros.S> |
| 12 | |
| 13 | /* |
| 14 | * Cortex-A15 support LPAE and Virtualization Extensions. |
| 15 | * Don't care if confiugration uses or not LPAE and VE. |
| 16 | * Therefore, where we don't check ARCH_IS_ARMV7_WITH_LPAE/VE |
| 17 | */ |
| 18 | |
| 19 | .macro assert_cache_enabled |
| 20 | #if ENABLE_ASSERTIONS |
| 21 | ldcopr r0, SCTLR |
| 22 | tst r0, #SCTLR_C_BIT |
| 23 | ASM_ASSERT(eq) |
| 24 | #endif |
| 25 | .endm |
| 26 | |
| 27 | func cortex_a15_disable_smp |
| 28 | ldcopr r0, ACTLR |
| 29 | bic r0, #CORTEX_A15_ACTLR_SMP_BIT |
| 30 | stcopr r0, ACTLR |
| 31 | isb |
Ambroise Vincent | d4a51eb | 2019-03-04 16:56:26 +0000 | [diff] [blame] | 32 | #if ERRATA_A15_816470 |
| 33 | /* |
| 34 | * Invalidate any TLB address |
| 35 | */ |
| 36 | mov r0, #0 |
| 37 | stcopr r0, TLBIMVA |
| 38 | #endif |
Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 39 | dsb sy |
| 40 | bx lr |
| 41 | endfunc cortex_a15_disable_smp |
| 42 | |
| 43 | func cortex_a15_enable_smp |
| 44 | ldcopr r0, ACTLR |
| 45 | orr r0, #CORTEX_A15_ACTLR_SMP_BIT |
| 46 | stcopr r0, ACTLR |
| 47 | isb |
| 48 | bx lr |
| 49 | endfunc cortex_a15_enable_smp |
| 50 | |
Ambroise Vincent | d4a51eb | 2019-03-04 16:56:26 +0000 | [diff] [blame] | 51 | /* ---------------------------------------------------- |
| 52 | * Errata Workaround for Cortex A15 Errata #816470. |
| 53 | * This applies only to revision >= r3p0 of Cortex A15. |
| 54 | * ---------------------------------------------------- |
| 55 | */ |
| 56 | func check_errata_816470 |
| 57 | /* |
| 58 | * Even though this is only needed for revision >= r3p0, it is always |
| 59 | * applied because of the low cost of the workaround. |
| 60 | */ |
| 61 | mov r0, #ERRATA_APPLIES |
| 62 | bx lr |
| 63 | endfunc check_errata_816470 |
| 64 | |
Sona Mathew | d7c07d1 | 2023-06-25 19:25:20 -0500 | [diff] [blame] | 65 | add_erratum_entry cortex_a15, ERRATUM(816470), ERRATA_A15_816470 |
Ambroise Vincent | 68b3812 | 2019-03-05 09:54:21 +0000 | [diff] [blame] | 66 | /* ---------------------------------------------------- |
| 67 | * Errata Workaround for Cortex A15 Errata #827671. |
| 68 | * This applies only to revision >= r3p0 of Cortex A15. |
| 69 | * Inputs: |
| 70 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 71 | * Shall clobber: r0-r3 |
| 72 | * ---------------------------------------------------- |
| 73 | */ |
| 74 | func errata_a15_827671_wa |
| 75 | /* |
| 76 | * Compare r0 against revision r3p0 |
| 77 | */ |
| 78 | mov r2, lr |
| 79 | bl check_errata_827671 |
| 80 | cmp r0, #ERRATA_NOT_APPLIES |
| 81 | beq 1f |
| 82 | ldcopr r0, CORTEX_A15_ACTLR2 |
| 83 | orr r0, #CORTEX_A15_ACTLR2_INV_DCC_BIT |
| 84 | stcopr r0, CORTEX_A15_ACTLR2 |
| 85 | isb |
| 86 | 1: |
| 87 | bx r2 |
| 88 | endfunc errata_a15_827671_wa |
| 89 | |
| 90 | func check_errata_827671 |
| 91 | mov r1, #0x30 |
| 92 | b cpu_rev_var_hs |
| 93 | endfunc check_errata_827671 |
| 94 | |
Sona Mathew | d7c07d1 | 2023-06-25 19:25:20 -0500 | [diff] [blame] | 95 | add_erratum_entry cortex_a15, ERRATUM(827671), ERRATA_A15_827671 |
| 96 | |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 97 | func check_errata_cve_2017_5715 |
| 98 | #if WORKAROUND_CVE_2017_5715 |
| 99 | mov r0, #ERRATA_APPLIES |
| 100 | #else |
| 101 | mov r0, #ERRATA_MISSING |
| 102 | #endif |
| 103 | bx lr |
| 104 | endfunc check_errata_cve_2017_5715 |
| 105 | |
Sona Mathew | d7c07d1 | 2023-06-25 19:25:20 -0500 | [diff] [blame] | 106 | add_erratum_entry cortex_a15, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
| 107 | |
John Powell | 7f7c6fa | 2022-04-14 19:10:17 -0500 | [diff] [blame] | 108 | func check_errata_cve_2022_23960 |
| 109 | #if WORKAROUND_CVE_2022_23960 |
| 110 | mov r0, #ERRATA_APPLIES |
| 111 | #else |
| 112 | mov r0, #ERRATA_MISSING |
| 113 | #endif |
| 114 | bx lr |
| 115 | endfunc check_errata_cve_2022_23960 |
| 116 | |
Sona Mathew | d7c07d1 | 2023-06-25 19:25:20 -0500 | [diff] [blame] | 117 | add_erratum_entry cortex_a15, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 118 | |
Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 119 | func cortex_a15_reset_func |
Ambroise Vincent | 68b3812 | 2019-03-05 09:54:21 +0000 | [diff] [blame] | 120 | mov r5, lr |
| 121 | bl cpu_get_rev_var |
| 122 | |
| 123 | #if ERRATA_A15_827671 |
| 124 | bl errata_a15_827671_wa |
| 125 | #endif |
| 126 | |
John Powell | 7f7c6fa | 2022-04-14 19:10:17 -0500 | [diff] [blame] | 127 | #if IMAGE_BL32 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 128 | ldcopr r0, ACTLR |
| 129 | orr r0, #CORTEX_A15_ACTLR_INV_BTB_BIT |
| 130 | stcopr r0, ACTLR |
John Powell | 7f7c6fa | 2022-04-14 19:10:17 -0500 | [diff] [blame] | 131 | ldr r0, =wa_cve_2017_5715_icache_inv_vbar |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 132 | stcopr r0, VBAR |
| 133 | stcopr r0, MVBAR |
| 134 | /* isb will be applied in the course of the reset func */ |
| 135 | #endif |
Ambroise Vincent | 68b3812 | 2019-03-05 09:54:21 +0000 | [diff] [blame] | 136 | |
| 137 | mov lr, r5 |
Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 138 | b cortex_a15_enable_smp |
| 139 | endfunc cortex_a15_reset_func |
| 140 | |
| 141 | func cortex_a15_core_pwr_dwn |
| 142 | push {r12, lr} |
| 143 | |
| 144 | assert_cache_enabled |
| 145 | |
| 146 | /* Flush L1 cache */ |
| 147 | mov r0, #DC_OP_CISW |
| 148 | bl dcsw_op_level1 |
| 149 | |
| 150 | /* Exit cluster coherency */ |
| 151 | pop {r12, lr} |
| 152 | b cortex_a15_disable_smp |
| 153 | endfunc cortex_a15_core_pwr_dwn |
| 154 | |
| 155 | func cortex_a15_cluster_pwr_dwn |
| 156 | push {r12, lr} |
| 157 | |
| 158 | assert_cache_enabled |
| 159 | |
| 160 | /* Flush L1 caches */ |
| 161 | mov r0, #DC_OP_CISW |
| 162 | bl dcsw_op_level1 |
| 163 | |
| 164 | bl plat_disable_acp |
| 165 | |
Stephan Gerhold | ed1cc20 | 2023-03-19 20:30:58 +0100 | [diff] [blame] | 166 | /* Flush L2 caches */ |
| 167 | mov r0, #DC_OP_CISW |
| 168 | bl dcsw_op_level2 |
| 169 | |
Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 170 | /* Exit cluster coherency */ |
| 171 | pop {r12, lr} |
| 172 | b cortex_a15_disable_smp |
| 173 | endfunc cortex_a15_cluster_pwr_dwn |
| 174 | |
Sona Mathew | d7c07d1 | 2023-06-25 19:25:20 -0500 | [diff] [blame] | 175 | errata_report_shim cortex_a15 |
| 176 | |
Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 177 | declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \ |
| 178 | cortex_a15_reset_func, \ |
| 179 | cortex_a15_core_pwr_dwn, \ |
| 180 | cortex_a15_cluster_pwr_dwn |