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git01.mediatek.com / filogic / atf / 90ce18f63012a1e7b1ba28d2432f5d90f61a22e3 / . / drivers / nxp / gpio / nxp_gpio.c
blob: 28c9db979b299b80a9308b1ead51fb89e96fb665 [file] [log] [blame]
Pankaj Guptab4806422020-12-09 14:02:39 +0530[diff] [blame]1/*
2 * Copyright 2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#include <common/debug.h>
9#include <lib/mmio.h>
10#include <nxp_gpio.h>
11
12static gpio_init_info_t *gpio_init_info;
13
14void gpio_init(gpio_init_info_t *gpio_init_data)
15{
16 gpio_init_info = gpio_init_data;
17}
18
19/* This function set GPIO pin for raising POVDD. */
20int set_gpio_bit(uint32_t *gpio_base_addr,
21 uint32_t bit_num)
22{
23 uint32_t val = 0U;
24 uint32_t *gpdir = NULL;
25 uint32_t *gpdat = NULL;
26
27 if (gpio_init_info == NULL) {
28 ERROR("GPIO is not initialized.\n");
29 return GPIO_FAILURE;
30 }
31
32 gpdir = gpio_base_addr + GPDIR_REG_OFFSET;
33 gpdat = gpio_base_addr + (GPDAT_REG_OFFSET >> 2);
34
35 /*
36 * Set the corresponding bit in direction register
37 * to configure the GPIO as output.
38 */
39 val = gpio_read32(gpdir);
40 val = val | bit_num;
41 gpio_write32(gpdir, val);
42
43 /* Set the corresponding bit in GPIO data register */
44 val = gpio_read32(gpdat);
45 val = val | bit_num;
46 gpio_write32(gpdat, val);
47
48 val = gpio_read32(gpdat);
49
50 if ((val & bit_num) == 0U) {
51 return GPIO_FAILURE;
52 }
53
54 return GPIO_SUCCESS;
55}
56
57/* This function reset GPIO pin set for raising POVDD. */
58int clr_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num)
59{
60 uint32_t val = 0U;
61 uint32_t *gpdir = NULL;
62 uint32_t *gpdat = NULL;
63
64
65 if (gpio_init_info == NULL) {
66 ERROR("GPIO is not initialized.\n");
67 return GPIO_FAILURE;
68 }
69
70 gpdir = gpio_base_addr + GPDIR_REG_OFFSET;
71 gpdat = gpio_base_addr + GPDAT_REG_OFFSET;
72
73 /*
74 * Reset the corresponding bit in direction and data register
75 * to configure the GPIO as input.
76 */
77 val = gpio_read32(gpdat);
78 val = val & ~(bit_num);
79 gpio_write32(gpdat, val);
80
81 val = gpio_read32(gpdat);
82
83 val = gpio_read32(gpdir);
84 val = val & ~(bit_num);
85 gpio_write32(gpdir, val);
86
87 val = gpio_read32(gpdat);
88
89 if ((val & bit_num) != 0U) {
90 return GPIO_FAILURE;
91 }
92
93 return GPIO_SUCCESS;
94}
95
96uint32_t *select_gpio_n_bitnum(uint32_t povdd_gpio, uint32_t *bit_num)
97{
98 uint32_t *ret_gpio;
99 uint32_t povdd_gpio_val = 0U;
100 uint32_t gpio_num = 0U;
101
102 if (gpio_init_info == NULL) {
103 ERROR("GPIO is not initialized.\n");
104 }
105 /*
106 * Subtract 1 from fuse_hdr povdd_gpio value as
107 * for 0x1 value, bit 0 is to be set
108 * for 0x20 value i.e 32, bit 31 i.e. 0x1f is to be set.
109 * 0x1f - 0x00 : GPIO_1
110 * 0x3f - 0x20 : GPIO_2
111 * 0x5f - 0x40 : GPIO_3
112 * 0x7f - 0x60 : GPIO_4
113 */
114 povdd_gpio_val = (povdd_gpio - 1U) & GPIO_SEL_MASK;
115
116 /* Right shift by 5 to divide by 32 */
117 gpio_num = povdd_gpio_val >> GPIO_ID_BASE_ADDR_SHIFT;
118 *bit_num = 1U << (GPIO_BITS_PER_BASE_REG
119 - (povdd_gpio_val & GPIO_BIT_MASK)
120 - 1U);
121
122 switch (gpio_num) {
123 case GPIO_0:
124 ret_gpio = (uint32_t *) gpio_init_info->gpio1_base_addr;
125 break;
126 case GPIO_1:
127 ret_gpio = (uint32_t *) gpio_init_info->gpio2_base_addr;
128 break;
129 case GPIO_2:
130 ret_gpio = (uint32_t *) gpio_init_info->gpio3_base_addr;
131 break;
132 case GPIO_3:
133 ret_gpio = (uint32_t *) gpio_init_info->gpio4_base_addr;
134 break;
135 default:
136 ret_gpio = NULL;
137 }
138
139 if (ret_gpio == NULL) {
140 INFO("GPIO_NUM = %d doesn't exist.\n", gpio_num);
141 }
142
143 return ret_gpio;
144}